Looking down Samsung's roadmap: 32 and 28 nm come into focus

In conversation with Samsung foundry vice president of technology Ana Hunter yesterday, some interesting details emerged about that company’s CMOS roadmap. One interesting point is the growing importance of half-node steps.

"Half-nodes aren’t just a way for the graphics-chip guys to reduce their costs any more," Hunter said. She went on to describe how a wider range of customers are looking to half-nodes, not only as a way to reduce die size on existing designs, but also as a way to adopt a process node as it matures and still get a slight advantage over early adopters in speed and power.

This has led to some rethinking about how to structure half-nodes, Hunter suggested. If the users are not confined to the most sophisticated early-adopters, it’s important to make the migration from the node to the half-node as easy as possible. Hence, for example,  TSMC’s announcement yesterday that their reference flow 9.0 provides transparent access to either the 45 nm process or the 40 nm half-node. "In general, customers will always have to recharacterize their design with the new libraries, but they shouldn’t have to redesign," Hunter said. "It should be an easy step." To this end, Samsung has decided to do the 32 nm PDK so that the rules are directly shrinkable to the planned 28 nm half-node.

The big changes, which to some extent will be visible to chip designers, are happening at 32 nm for Samsung. That’s where the company will switch to a high-k/metal-gate gate stack, and that’s the node where Samsung is likely to introduce double-patterning on a few critical layers. The half-step down to 28 will be simply a shrink, with no major technology changes involved, just as TSMC’s 40 nm is a shrink of its 45 nm rules.

In some ways, the choice to go with high-k/metal-gate at 32 nm will make the shrink strategy more viable. The new technology not only reduces leakage, vastly mitigating energy-management issues, but, according to Hunter, it also really improves threshold-voltage matching in the 6T SRAM cell. This has meant that there is more margin to play with in the 32 nm cell, and a shrink to 28 is unlikely to break anything. Since the SRAM cell tends to be the canary in the mine for a new process, this bodes well for the entire half-node.

So what about 40 nm? Hunter says that Samsung is still debating whether to offer a 40 nm option, or simply to move customers directly to 32 nm. As much as anything else it’s a matter of engineering resources. The 32 nm process is tantalizingly close, and pulling process engineers to productize 40 nm could soften the focus on 32 nm (no litho puns intended.) And with Samsung’s bet on high-k looking like it’s panning out, 32 nm could be the show-stopper for Samsung.