Multi-voltage low-power design: someone has to pay the piper

There has been a huge amount written in the last year about the use of voltage islands, power gating and even dynamic voltage adjustment as tools for reducing the energy consumption of SoCs. Early on the talk was more conceptual, as only teams with the resources to develop their own tools could actually try such techniques. Now, commercial tool chains are beginning to support these techniques at least tentatively, with automatic layout and supply routing for voltage islands, automatic level converter insertion and so on, and the conversation is moving on toward evaluation of the new tools and practical experiences.

But there is another part of the conversation that needs to happen as well. That is the impact of these techniques at the system level. It’s wonderful if SoC designers can use every trick in the book and reduce energy consumption in the chip by 39 percent. But what is every trick in the book doing to the board-level design?

I was rather forced to think about this the other day when looking at a smartphone reference design. The board was build around one of those elegant all-in-one application processor SoCs that combines CPU, local memory and every interface controller you can think of. But the result was not a small, sparsely-populated board by any means. And a lot of the chip population could be traced back to the aggressive power management in the SoC.

Begin with the obvious. If you use multiple voltage islands in the SoC, unless you provide on-chip regulators, you will create the need for multiple supply voltages on the board. Unless you are so big and powerful that you can have linear chip companies make a multi-voltage regulator IC just for you, that probably means multiple regulators to deal with multiple voltages at different loads and different dynamics. But this also probably means some sort of state machine—probably a microcontroller—just to sequence the power supplies so that they come up and go down in the correct sequence to not fry anything or create spurious states. And that, for anyone who hasn’t tried it, is a serious design problem all by itself, requiring a detailed understanding of a large portion of both the digital and analog subsystems.

Then there is the problem of level translators. In this particular case, the low I/O voltages chosen by the SoC designers didn’t happen to match the low I/O voltages chosen by some of the external chip designers. So the board had a fair number of level-translating buffer chips scattered about. This is not to mention the power supply issues of Ethernet, USB, and disk interfaces.

Finally, there is the question of dynamic voltage control, which didn’t happen to be an issue on this particular board. Take a look at ARM’s (see for instance here) or National Semiconductor’s (see here) reference design work on their intelligent energy management initiative to get some idea of the board-level complexity this can entail—now imagine it without a specialized power controller chip such as the one National provides for ARM CPUs.

Not only can aggressive power management at the chip level significantly complicate the board-level design and run up the bill-of-materials cost, I suspect that one would have to go all the way to usage scenario analysis to prove that the energy savings in the SoC really outweighed the energy costs outside the chip. When the end customer only cares about features, weight, and battery life, that’s a significant concern.