Heard at the GSA IP Conference: IP porting influences process selection

A panel of experts on the creation and porting of silicon intellectual property (IP) discussed porting IP to advanced processes—what’s involved, and what IP users need to know about it—in the afternoon session at the Global Semiconductor Association IP Conference in Santa Clara, California today. The conclusion was that 65 nm and 45 nm have changed IP porting for ever, and it is vital for IP users to understand how.

In this context, IP is not all the same, of course. Joachim Kunkel, vice president and general manager of the Solutions Group at Synopsys, pointed out that porting soft IP from one process to another is not the same order of problem as porting hard IP. "Generally, the kinds of soft IP we get involved with don’t push the process technology that hard," Kunkel explained. "So we can rely on the tool flow, good libraries, and design-rule checks to make the results come out right in a new process." But Kunkel did say that increased leakage current, and the expectation that early adopters of 65 or 45 would be power-conscious users, meant that even soft IP required more attention to power management. "So far, though, we have not seen a case where we had to go back and rearchitect the RTL to get the result we wanted in a new process," Kunkel said.

For hard IP, however, Kunkel said the situation was very different. "Porting to 65 nm was for the most part more of the same we’d experienced porting to 90," he related. "Well-proximity effects were greater, and variations were greater. But at 45 nm, it’s very different. All of a sudden you only have two or three devices to choose from instead of a dozen. Layout is much more restrictive. And 32 nm is even more restrictive than 45."

John Maneatis, president of PLL vendor TrueCircuits, described some of the issues from a precision-analog viewpoint. "You are always dealing with an increasing ratio of threshold voltage to supply voltage," he said, "and constantly increasing variations. And while at 65 nm there were some places where design constraints became an issue, the rules become really strict at 45 nm."

In contrast, Emmanuel Riou, RF engineering manager at Wipro NewLogic, gave a good-news/bad-news scenario. "For RF designers, the loss of transistors to choose from is a problem. You have to give up transistor choices, but you still have to find 10 or 15 dBM of gain somewhere. The good news is that the little transistors are much faster—especially the PMOS transistors. So we are starting to see circuit architectures that exploit the speed of the PMOS."

Asked how these new challenges had changed the job of porting IP, the panelists mostly agreed with ARM Fellow Rob Aitken, who said that the nature of the job had changed. "When we are moving a piece of IP from one foundry to another at the same process node, it is still porting," Aitken said. "If we are moving it to a new node, it is more like a redesign."

Maneatis described  the concept of architecting IP to be robust in the face not only of process variations, but of model inaccuracies and even differences between processes. He pointed out that if you can identify the ways in which the next process is likely to be different—and they are mostly predictable—you can reduce the amount of new design work required for the next process node. Kunkel added that it was increasingly common to see additional circuitry in IP that allowed the electrical parameters to be adjusted via registers, so that the circuit could be tuned to deal with variations or new conditions.

But verification of the ported design was another matter, the panelists said. Here there are two issues to face. First, with increasing variations there are many more corners that must be investigated during verification, and larger process variations that must be considered during extraction. So there’s a lot more simulation to do. Monte Carlo analysis has become virtually mandatory for many. And many circuits are becoming so complex and tightly-coupled that it requires art to get a simulation to converge at all.

Second, since there is increasing pressure to make IP available, much of the design and verification must be done while the device and process models in the PDK are still changing rapidly. This latter point Maneatis related back to robust circuit design and the importance of having a powerful Monte Carlo simulation strategy. He suggested that you could reduce the sensitivity of the design to model inaccuracies just as you could reduce its sensitivity to process variations.

Asked, given the preceding discussion, what advice they would give to IP users, the panelists sketched a picture of an IP-evaluating design team nearly merged with the design team that ported the IP. "I would say at a minimum, know whether the IP has been used in this process in a similar configuration to yours," Aitken said. Kunkel added "I would say always get references from someone who has used the IP before. If you really want to know what to expect from a piece of IP at a new node, and no one else has used it yet, you pretty much have to go through the IP designers’ engineering process in detail. It’s like a design review."

Maneatis agreed. "It’s not enough to look at test chips any more. Test chips may not represent the way you will use the IP. But more important, at these advanced nodes, test chips don’t tell you anything about yield. You just can’t tell what the yield issues will be."

Kunkel observed that this level of IP evaluation sounded like a lot of effort. "But you don’t have to do this every time you evaluate a new piece of IP. Once you have worked with a vendor and know their process, you don’t usually have repeat all the work again."