D2S replicates direct-write e-beam scheme in Europe, moves to 45 and 32 nm

D2S, the company that enabled Fujitsu’s direct-write e-beam production system for fast-turn, moderate-volume 65 nm chips, has announced a collaboration to produce a similar design flow in Europe for 45 nm and 32 nm ICs. Working with chip research consortium CEA/Leti in Grenoble, France, and with e-beam system vendor Vistec Electron Beam in Jena, Germany, D2S intends to produce design libraries and software that will enable a recently-announced Vistec character-writing e-beam system to directly expose wafers for critical transistor-level layers.

According to D2S CEO Aki Fujimura, the design flow remains the same for users, and structurally similar for D2S engineers, as the flow used at Fujitsu. "It’s like porting a video game to a different game console," Fujimura said. "The game stays the same, but some of the code has to change. You make different trade-offs for different e-beam machines."

The key to making the direct-write process fast enough for use in production is the ability of the variable-shaped-beam Vistec system to expose several features—for instance several contacts on the contact layer—with the same shot, according to Vistec Electron Beam general manager Wolfgang Dorl. This requires close collaboration between the Vistec engineers, who understand the character-forming capabilities of their system, and the D2S designers, who must design their cell libraries using patterns that the Vistec system can produce. "If you are very clever with cell layout, you can find ways to reuse the same e-beam character over and over for different kinds of cells," Fujimura explained. The goal is to minimize the number of shots exposed by the e-beam system to something significantly less than the number of features.

The collaboration between Vistec, D2S, and Leti should produce exposed wafers within the next few months, according to Dorl. These would presumably be on the 45 nm process ST Microelectronics runs at Crolles, France, and would lead to a full production capability for the e-beam system on that process.

In production mode, the chip design team divides up the tape-out of a new chip. The less critical layers go to a conventional mask shop, while the most critical layers—the ones that would normally require the most OPC work, mask inspection, and repair—go to D2S. D2S then converts the mask data for these layers into command files to the e-beam system.

In the fab, the e-beam system directly exposes the wafers for each critical layer. After each exposure the wafer is developed and processed normally. After the critical layers—such as source/drain diffusions, channel implant masks, contacts, and perhaps metal-1—have been processed, the wafer goes into a standard flow using 193 nm lithography. By eliminating the mask-making steps for the most critical layers, the D2S approach claims to significantly shorten the turn-around time and reduce the NRE at advanced process nodes. This makes 65 nm, and now with the new agreement 45 nm and potentially 32 nm, nodes feasible for prototyping and moderate production runs for the first time.