Texas Instruments lifts the lid on OMAP 4, and shows architectural evolution

TI rolled out their first OMAP-4 SoC today, demonstrating once again that the company believes in the smart phone market as a path through the recession. But aside from what the chip might say about the company’s business strategy, it does make several clear statements about integration strategy and architectural thinking at the Texas giant.

First, it’s clear that TI has bought into mainstream thinking about media SoCs. Far from being a vehicle for its proprietary DSP architecture, the OMAP-4 SoC is more of a peer-processing cluster, with almost a laundry list of processing cores: two ARM Cortex A9 MP cores arranged as a symmetric multiprocessing pair; a media engine with a central DSP core "based on"—to quote TI’s release—their C64xx architecture; a cluster of dedicated, but presumably still programmable, accelerators surrounding the DSP core; a still-image processor block; and a dedicated 2D/3D graphics core. Unmentioned in the laundry list but still vital to the operation of the chip are the substantial amounts of on-chip RAM necessary to keep this powerful a cluster of processors from lurching into permanent bus lock-up. That includes a full MegaByte of L2 cache shared by the two Cortex A9s.

Further emphasis on bandwidth shows up in between the lines of TI’s description. The chip has a pair of low-powerDDR2 DRAM ports to support the bandwidth requirements of all those processors even after the on-chip RAM takes the edge off their hunger. And—notice how packaging is seeping into architectural decisions in the hand-held space—the chip is designed from the outset to be stacked with external DRAM, using TI’s internal package-over-package technology. That should reduce the power consumption of the system at least somewhat by minimizing the capacitance on the DDR clock and signal lines.

If all this sounds more like a home media center than a smart-phone application processor, that tells us something about TI’s notion of use models for LTE smart-phones. The company says that the SoC will support 1080p record and playback at 30 frames/second, still photography at up to 20 Mpixels with no more than 1 second inter-frame latency, and interactive 3D-graphic user interfaces—presumably taking the iPhone touch-screen metaphor into 3D rendering.

All of this brings up another thing the design tells us about TI’s SoC efforts: their attitude toward power management. Rather than minimizing power consumption with extensive use of dedicated hardware, TI has chosen to keep much of the computing in the fully-programmable ARM and DSP cores, saving their dedicated hard macros for the nastiest inner loops. This has obvious advantages in giving systems developers a lot of scope to differentiate themselves in software, but it raises an equally obvious flag about power consumption: software is not the most energy-efficient way to do anything.

The architects have attempted to overcome this problem with extremely aggressive hardware/software power management. The design uses a battery of techniques, including dynamic voltage-frequency scaling on the ARMs and unspecified other cores, and dynamic power gating on the accelerators. According to TI platform marketing manager Robert Tolbert the chip is a maze of voltage domains, with no functional block getting a higher operating voltage than it needs to meet performance requirements. But within these voltage islands is a finer-grained network of power-gating regions, allowing TI to completely power-down, and hence zero the leakage current on, sub-blocks that are not in use in the current operating mode.

Finally, the design says something about TI’s emerging fab-lite foundry strategy. This first OMAP-4 SoC is done in a 45 nm process and may or may not intended to be built within TI. Tolbert was quite non-directive about that. But he did say that the SoC will not even sample until the second half of this year, and won’t be in production until the second half of 2010. This puts the chip well behind TI’s previously-announced schedule for internal 45 nm production. Also, by then, leading foundry customers who are also salivating over the smart-phone space may consider 45 nm to be a legacy process. The schedule also appears to rule out TSMC as a foundry partner, since TSMC is reportedly determined to move all its foundry business from 45 nm to the 40 nm half node before next year.

That raises a final question. No one can doubt TI’s experience in the media-processing and mobile handset spaces, nor their ability to assemble a hardware, tool, and software infrastructure around an OMAP platform. Given the hints we have about the OMAP-4 power management, it appears that the company has done its homework in this area as well. But will the company stumble on one of its greatest traditional strengths—manufacturing–as it shifts from internal to external fabs in the teeth of a recession? It’s a critical question.