Synopsys reorganizes extraction offerings: Star RC becomes trinary system

Synopsys is quietly reorganizing its Star RC extraction tool into a set of three products. The current Star RC will become a midrange product, aimed at rapid RC extraction of full chips and very large IP blocks. A level above midrange will be Star RC Ultra, with a growing list of advanced capabilities aimed at high-end designs. And today, the company introduced Star RC Custom, for smaller design chunks and greater accuracy.

Ultra will offer statistical extraction: the ability to estimate not just mean values but the statistical distributions for parasitic Rs and Cs. It turns out that Synopsys’s statistical timing engine has for some time had the ability to use this statistical parasitic data, but to date most users have ignored the capability, focusing instead on active-device parameter statistics. Of course the statistical extraction data can be used to launch Monte Carlo runs for analog simulations.

Additional features in the Ultra package will include a link to a CMP simulation tool that will give Ultra extractions a tighter window on interconnect variations due to systematic CMP effects. Another bit, further in the future apparently, will support extraction from multi-die structures such as wirebonded stacked dice or dice connected with through-silicon vias. Ultra is actually available now if you know the right people, and will see general availability in December.

This morning, Synopsys introduced the third tine of their extraction trident, Star RC Custom. This version is intended for interactive design of custom blocks and for cell or IP characterization. Consequently, it emphasizes accuracy over capacity, while still recognizing that even a cell library has to have a reasonable extraction time and manageable simulation runs. To this end, Custom has three categories of features that distinguish it from the original-flavor Star RC.

The first of these categories is in the extraction engines themselves. Custom employs the Star RCXT ScanBand engine, which apparently is based on a pretty standard table-driven algorithm. Synopsys claims this engine is capable of traversing 10 million nets overnight, extracting with 5 percent accuracy. But Custom also integrates the Raphael fast field solver engine, which is about three orders of magnitude slower but capable of far greater accuracy on structures that give problems to table-driven extractors.

Increasingly, such structures are showing up in the contact layer on 40-45nm processes, according to Robert Hoogenstryd, director of marketing at Synopsys. Some of these structures are so small that tiny absolute errors in parasitic capacitance are large percentage errors on low-impedance nodes. At least for now, it is up to the user to direct Star RC Custom whether to use ScanBand or Raphael on a given structure.

Features in the second category work with Synopsys’s transistor-level simulator, CustomSim, to slash simulation times by reducing the complexity of the extracted models. These features appear to be aimed primarily at digital circuits, but there’s nothing here that wouldn’t apply in principle to analog designs. It’s just not clear that a senior analog designer would take them at face value.

Hoogenstryd cited three specific techniques in this area. First, Custom can, in effect, keep a back-of-the-envelope sensitivity analysis, and simply remove parasitics from the device models if they are not going to significantly affect the net. Hoogenstryd offered one example in which extracting only contact-to-gate parasitics and grounding all the other parasitic caps in the transistor models resulted in a two percent error in the calculated delay compared to a full simulation, but a factor of eight reduction in simulation time.

Another technique uses activity files to identify the level of activity on each node, and to increase the level of extraction detail on the most active nodes while turning down the effort on the least-active ones. This can produce an order-of-magnitude speed-up in simulation, Hoogenstryd said. It’s impact on rarely-used nodes with near-zero slack, or for that matter its meaning for analog designs, seem unclear.

Finally, Custom can decide whether to use hierarchical back-annotation or whether to flatten a portion of the design. Hoogenstryd said that simply employing hierarchy whenever possible can accelerate simulation a lot, but it can also introduce errors when different instances of the same structure are not, in fact, in equivalent contexts, and will have different parasitics. So Custom uses an algorithm to estimate the accuracy of employing hierarchy. The result Synopsys claims is a significant factor speed-up in simulation with minimal impact on accuracy.

The third feature set revolves around integration of Star RC Custom into the Synopsys Custom Designer cockpit. You can set up extractions, run Star RC Custom, and explore the results directly from Custom Designer, in the metaphor of the netlist or physical layout. The impact on designer time and aggravation is obvious.

The resulting Star RC Custom package, Hoogenstryd said, should offer both speed and accuracy to cell and IP designers. Custom, like Ultra, will be generally available in December. Customers can swap licenses between the three Star RC versions, at fixed ratios, to get just the right tool set for each point in their design cycle.