SpectraLinear clock generator reflects the complexity of Intel Calpella motherboards
A new clock generator IC from SpectraLinear opens a window on an interesting comparison between the problem of generating and distributing clocks for a mobile, media-centric personal computer motherboard and doing clock tree synthesis on an SoC. "In the board world, the PC motherboard is kind of unique because there are so many clock requirements," observes SpectraLinear VP and business-unit manager Elie Ayache. There are CPU clocks, I/O clocks, clocks for PCI-Express, clocks for SATA interfaces, clocks for video, clocks for HDMI and Display-Port, clocks for DDR3, reference clocks—you name it. But that same trait makes the PC motherboard rather like a modern media SoC.
The big difference is that, if you buy an off-the-shelf clock generator chip, there is a problem with the step in the board design process that corresponds to clock-tree synthesis on the SoC. Once you have the board layout, know the loads on the various clocks, and can work out the necessary clock skews, rise and fall times, impedances, and so on, how do you adjust them? The answer is that the clock generator chip must be highly configurable.
But that in itself raises a problem, according to SpectraLinear vice president of engineering Greg Richmond. You need to avoid having a special power-up-and-configure cycle for the clock chip, and the bill-of-materials budget for a typical motherboard won’t tolerate an additional PROM just to initialize the clocks. So the configuration information for the clock chip should be on the chip. Yet the cost limit for these chips precludes either the use of non-CMOS technology to provide Flash cells or use of CMOS-compatible non-volatile reprogrammable memory to store the configuration data. So SpectraLinear settled on a large amount of OTP memory that they configure at the factory for a particular customer order, along with i²C-programmable registers for parameters that can change during operation. The result is a very small die and a high degree of configurability.
It is that configurability that carries the weight of tuning the clocks to the motherboard, in much the same way that clock-tree synthesis tunes the clock network on a chip to its loads. In the SpectraLinear device—the SL28748, by the way—most of the characteristics of each clock output are configurable. For instance, the output impedance of each output is programmable, as are the overshoot and undershoot characteristics. The rise/fall time of each output can be set to any one of eight steps, without altering the output impedance. (It’s done by adjusting the pre-drive stage rather than the output stage, if you were curious.) For clocks with differential outputs, the skew between the True and Complement signals is configurable, so you can minimize common-mode due to differences in the two traces.
Like pretty much all modern board-level clock generators, this device provides spread-spectrum signal generation in the PLLs. But there are some differences that are rather unique to the PC world—and that might be useful for SoC designers as well. For example, different devices on the PC motherboard have different jitter tolerances, and hence require different spreading profiles. So the chip provides independently-configurable triangular profiles for each of its spread-spectrum PLLs. But the triangular profiles are also fundamentally different from conventional profiles. "It turns out that conventional spread-spectrum profiles put harmonics right in the jitter window for PCI Express gen-2," Richmond said. "So we altered the profiles to move the harmonics to someplace where they wouldn’t interfere with PCI."
One of the issues with the Calpella design is the need to switch frequencies on the fly. This means that while some of the clocks have to remain on-frequency, others have to smoothly move from one frequency to another without glitching. This in itself provides an interesting exercise in PLL design, since you can’t allow the loop to unlock as the frequency is ramping.
And of course, since Calpella is a mobile platform, there is the matter of power management. Richmond said that the SpectraLinear design team attacked every aspect of power dissipation in the chip, from the core to the outputs. The 0.18-micron chip has its own multiple voltage regulators running off the 3.3V input supply, allowing SpectraLinear to turn down the voltage to each VCO until the oscillator just locks at the required frequency. Add to that the ability to adjust the output voltages down to 1.05V and to tune each I/O to its actual environment on the board, and you get substantial power savings—up to 50 percent compared to alternative approaches, according to the company. The preliminary datasheet claims under 100 mA dynamic current on the 3.3V supply under full load.
The flexibility of the chip illustrates to what extend board-level design is approaching the clock generation and distribution challenges that designers of media SoCs have been facing for some time. It’s an interesting convergence.
