Intel's Borkar hints at future of SoC architecture and semiconductor test

In a plenary talk at the International Test Conference this morning Intel fellow Shekhar Borkar offered a tightly-reasoned description of how IC architectures will look in a few years, with some observations about the future these architectures imply for test engineers. The talk certainly represented the views of Intel’s director of microprocessor technology, and may indicate the general direction of thinking within the company.

Starting with the familiar, Borkar discussed just what kind of chip one could build today, and tomorrow, with a power budget of 65W. Today, he said, you could combine about 50M logic gates with about 6 MB of cache: a typical dual-core high-end CPU chip. But ten years from now, Borkar warned, scaling in both energy-efficiency and delay will have slowed down considerably, while the magnitude of process variations will have increased. At that point, the same power budget would buy you only three times more logic transistors, and ten times more cache: not a sufficient improvement for a decade’s work.

The alternative, Borkar said, was to move the logic transistors off their current scaling curve and onto the SRAM power-scaling curve. To do that, he said, would require a new approach to logic design: what he called near-threshold logic. By designing relatively small processing cores operating at very near their threshold voltage and by employing fine-grained voltage-frequency scaling, Borkar said, you could design cores that operated near the theoretical peak of energy efficiency. At this high efficiency you could get many more logic transistors on the 65W die.

But this would require an entirely new approach to design, because as the supply voltage approaches the threshold voltage the relative magnitude of process variations grows rapidly to the point that you can no longer count on the quality of the transistors, and you have little margin to protect against soft errors. In this new world, Borkar suggested, many things would change, including on-chip interconnect architectures, design flows, and—of greatest interest to the ITC audience—test.

For interconnects, Borkar questioned the growing use of packet-based networks-on-chip. He pointed out that in advanced geometries, the delay incurred in the NOC router is significantly greater than the typical wire delays for point-to-point routing. So Borkar suggested an interconnect architecture that would see his previously-mentioned small processors connected into clusters by wide busses, with either another level of bus or possibly a packet-switched network interconnecting the clusters.

On the design-flow question, Borkar cited a recent paper by Toshiba, in which they described their reimplementation of IBM’s Cell processor. Using conventional synthesis tools and what Borkar described as "a small cell library" Toshiba was able to produce a Cell core 30 percent smaller, and with 28 percent shorter mean wire length, than IBM’s custom design. Pointing out that not only is the number of design rules growing exponentially, but the number of operations per rule is growing exponentially, Borkar asked if it even makes sense to attempt manual design at advanced process nodes, or whether the problem is now so complex that synthesis will beat a custom design team by the time all the rule violations are repaired.

Finally, Borkar pulled together his observations to paint a picture of the future for semiconductor test. He said that the chip of the future would be a cluster of relatively small, soft IP cores. Further, he said, data suggest that at advanced nodes aging effects will be significantly worse than today, and burn-in a less effective predictor of reliability over time. Process variations will be extreme by today’s standards, and the circuits, operating at near their threshold voltages, will be subject to soft errors.

"In this environment, factory testing is meaningless," Borkar said. "We have to get beyond the notion of testability and instead create designs that can self-test and reconfigure themselves continuously." Having mapped out what appears to be an inevitable merger of test engineering into design engineering, the Intel fellow ended his talk.