Calypto to power-management experts: have it your way

Calypto has for some time now successfully levered their core technology—sequential analysis of synchronous logic circuits—into a full suite of tools to reduce power consumption. Analyzing your RTL, the Calypto tools identify opportunities to apply fine-grained clock gating and fine-grained use of sleep modes in memory instances. The tools then reorganize the RTL if necessary, insert enable signals into the code, and if you wish provide a formal equivalence check to make sure they didn’t break anything. All of this takes place before synthesis, where in theory you still have the most leverage over active and leakage power. In fact, the company claims, the tools can reduce power by up to 60 percent.

All this should be great news for teams working on power-constrained designs. And Calypto CEO Tom Sandoval says that he has seen a rather dramatic surge of interest in the products starting about last October, when chip-design activity began to recover from its economically-induced coma. But ironically, the one group that is in the best position to appreciate what the Calypto tools do—power-management experts—has had an issue.

The sticking point is automation. RTL gurus don’t want a tool taking liberties with their code, even if it does the right thing. So today, Calypto is announcing an additional flow based on release 3.1 of its PowerPro package. In this flow, called PowerAdvisor, the tools analyze your RTL, but instead of making edits to the code automatically PowerAdvisor makes recommendations to you, without altering your code.

Sandoval said the flow offers three categories of information in its reports. First, the analyzer generates clock-gate-enable and memory-mode-enable expressions based on your existing RTL. You can review these at your leisure and drop the ones you like directly into your code. This is in essence a manual version of the existing PowerPro CG and MG tools. Second, the analyzer suggests changes to the existing RTL that would make possible further clock- or memory-gating opportunities. For example, the tool might suggest importing a mode-control signal from up-stream, making it possible to gate the clock on a register when there is no activity on the block’s inputs. If you like PowerAdvisor’s suggestions you can modify your RTL and then rerun PowerAdvisor, which will generate the correct enabling expressions.

Third, PowerAdvisor will suggest changes to your microarchitecture that would open up even more gating opportunities. For example, the tool spots registers that rarely change but are not efficiently clock-gated, and registers that toggle often in situations where their outputs don’t actually affect other circuits. You can look into these areas of the design and, if it’s appropriate, reorganize them, then return to PowerAdvisor to get the enable expressions. In all these cases PowerAdvisor generates a table, hyperlinked to its suggestions, that estimates the size of the power savings from each recommendation.

On any one block, PowerAdvisor probably isn’t doing anything a skilled power-management engineer wouldn’t think of with a bit of effort. But it’s probably going to find many more opportunities than a human would have time to ponder under any realistic design schedule. If the tool is available, why not let it do the detailed hunting and finding, and spend your expert time in other areas not yet subject to automation, such as organizing the design to minimize signal activity?