PHY IP: the last frontier of configurability?

An IP announcement by LSI last week highlights several key issues in the design of a modern serial interface PHY. The block, the PHY 9500, is the fast serial interface member of a complete library of critical IP blocks for implementing mass storage controller SoCs, the TrueStore family. The PHY 9500 supports SATA 6G, SAS 6G, and Fibre Channel 4.25G interfaces from one block.

The first issue worth noting is this multi-standard flexibility. The three interfaces are all fast serial ports, but they are rather different in electrical characteristics, application environment, and specifications. A piece of IP to serve them all would require a good deal of configurability, and this sort of design-time malleability seems to be a recurring theme in fast interface IP of late. Despite the design challenges, verification issues, and potential complexity of integration, stretching one piece of hard IP across a range of behaviors seems to be where the market is going.

To do this is not trivial. Obviously you need to be able to adjust parameters like output drive strength, topology of termination networks, and local oscillator frequencies to cover all the necessary operating points. You also may need adjustable transmitter preemphasis and selectable receiver equalization.

In the case of the LSI part, it won’t do to just design the equalizer for the worst-case applications environment. LSI product marketing manager Ishtiaque Mohammad said that for the 9500, the worst case is easy to identify. "Enterprise SAS environments have incredible noise issues," he said. But he also pointed out that you can’t just design for SAS and let everyone else have vastly better-than-required equalization. In the world of digital equalizers, strength costs power, and most of these applications are power-sensitive. So LSI’s designers opted for a configurable multi-tap digital feedback equalizer in which you can disable taps as the noise environment and eye-opening requirements allow to reduce operating power.

A second point illustrated by the 9500, despite what we just said about equalizers, is the gradual shift of signal processing back to the analog domain. In this block, the transmitter preemphasis is done in analog, rather than on the digital side. "It’s a lower-power solution than digital," Mohammad explained.

Finally, a point about on-board diagnostics and system monitoring. The 9500 offers LSI’s Eye-Q monitor, essentially a block within the receiver chain that collects data on the receiver performance and sends it out through a JTAG port. Among other things, the block can build its own eye diagrams. So it becomes possible for the SoC to monitor receiver performance with substantially less overhead.

This move to integrate more diagnostic and system management capability into PHYs appears to be gathering speed across the industry. Early last week Phyworks, which builds PHY parts at the chip level, introduced a 10G CMOS transceiver chip for optical interface applications that includes both a temperature-sensing circuit–designed to work with an external resistor–and a circuit to provide digital readings of temperature, transmit power, receive power, bias current and supply voltage. This substantially reduces the computing power and peripheral circuitry necessary to monitor the operation of the PHY, according to Phyworks CEO Stephen King, and has direct leverage over the cost of interface modules for 10Gbit passive optical networks.

The move to bring configurability and on-board monitoring into PHY IP, as well as the shift back to analog for some signal-processing, seem to indicate that CMOS PHY designers are gaining enough confidence to directly attack system-level needs beyond just the specs of the interfaces they are serving. These steps add complexity to the design, but potentially simplify the problem for IP integrators and systems developers by a significant margin.