SiP and SoC: conference takes on modeling, design and test issues for multi-die packages

Intuitively, a design team’s use of on-chip integration and in-package integration ought to be a matter of system partitioning—a question decided wholly on issues such as the functional and process requirements of individual blocks and the demands of the interfaces between them. Placing a block on one die or another should be a matter of deductive reason.

But that is far from the case today. Even though technically system-in-package technology allows designers to tightly couple multiple dice within a single-die footprint, and to achieve very high bandwidths at low transport energy between these dice, that just isn’t real life for many teams. The reasons are manifold. Among them: SiP design technology is unfamiliar to many teams; models, tools and flows are very different when a path goes between dice than when it goes between blocks on a die, and there is no co-design methodology; the availability of known good dice to integrate into an SiP is usually limited, and the actual quality problematic; and SiP technology places huge demands on design for testability at the packaged assembly level.

The urgency of these problems has been underlined by a recent exercise within the Fabless Semiconductor Association. According to ASE Group senior technical advisor Bill Chen, the FSA last year convened its technical advisory board to identify the most pressing technical issues facing members in 2007. The board’s list was put out to member companies for a vote, and the two top vote-getters were co-design of SiPs with SoCs and design for testability of SiPs.

This result led the FSA to organize a two-day conference, starting tomorrow at the San Jose Doubletree, on the issues surrounding SiP design from the point of view of fabless chip design teams—that is, teams that are unlikely to have in-house package assembly and test capability. Chen says that the goal of this first conference is simply to get knowledgeable vendors and users together to establish a baseline of what the current state of the technology is, who is working on what, and what remains to be done.

Given the tremendous potential SiP technology has for highly integrated systems and the neglect it seems to be attracting from model developers and tool vendors, this seems like one of the more important conferences of the year. And the fact that it requires a conference just to figure out who’s on first is an indicator of how much of the hard work remains to be done in this area.