Ciranova automates analog device placement

After the well-publicized failures of a few years ago, the EDA industry is approaching the whole area of analog design automation with a good deal of care. No one is going around these days suggesting that it’s feasible to synthesize full, parametrically correct and DRC-compliant analog circuits from a set of equations or a SPICE netlist. But there is continual progress in automating the individual steps in the design process.

Ciranova, with its deep background in this world of p-cells, is announcing one such step today. The company is launching Helix: an automated placement tool. Helix is said to accept a SPICE netlist, a user-generated constraints file, a p-cell or PyCell library, and a technology description file, and produce a production-quality device-level placement in a matter of minutes to tens of minutes, depending on the complexity of the circuit.

The result, Ciranova says, will be DRC-clean, and will comply with both the user-specified circuit constraints and all process-related device constraints. And the layout quality, the company boasts, is near or equivalent to skilled hand-crafted placement. In fact, at 65 nm and below, Helix may do a better job than a human can hope for in a reasonable amount of time.

Ciranova says that Helix is a drop-in change to the analog design flow, working with the user’s preferred circuit design flow and with any major analog back-end flow, including Cadence Virtuoso, SpringSoft Laker, or Magma Titan.

The obvious advantage is in design time, automating what has been a manual process highly dependent on user experience. But there are other advantages as well. Since the target process is represented only by one technology file, Helix makes the entire analog design flow significantly more portable. If you want to target a different process, have the circuit designers check the devices for resizing opportunities, then plug in the new process technology file and run a new placement.

A less obvious advantage, according to Ciranova vice president of marketing Dave Millman, is that the tool makes the entire analog flow more robust. "Today, the way the circuit designer communicates intent to the layout team is typically a lot of pencil notes on a copy of the schematic," Millman says. "Q14 and Q16 need to match. Keep the inputs on the left side of the block. Keep the outputs away from each other." This fragile source document easily gets lost, taking a lot of the design intent with it, and making reuse of the circuit design a much more difficult problem. By capturing this data in a constraints file (in a Ciranova proprietary format) this relative-geometry data becomes an archivable part of the design.

Another point the Ciranova folks make is that as the process gets into the 90, 65, or 45 nm range, automated placement becomes increasingly important. Not only does the number of devices tend to increase, as designers throw transistors at the challenges of fine-geometry analog, but the number and complexity of layout constraints grows enormously. This is even the case when the design is using non-minimum-geometry devices, Millman argues. "A surprising number of inter-layer design rules affect larger devices just as much as they affect minimum-geometry ones. We are finding from customer experience that a DRC-aware automated placement below 130 nm may actually produce a smaller area than a very good manual placement, just because the tangle of design rules gets handled automatically."

Getting these rules into Helix in the first place is apparently  no picnic, however. CEO Eric Filseth explains that the first step is knowing where to look. "Process technology files in the PDK may or may not have enough data to tell you how to place devices. But the DRC decks usually do have enough data. The problem is getting it out. It’s in the DRC deck in the form of checks, but we need to turn those checks into construction rules. It’s a complex task, and we usually end up collaborating with the foundry and our customer to get it done."

The big take-away from Ciranova’s point of view is speeding up the analog placement task. But Filseth speculates that in addition to accelerating today’s flow, Helix could help the emergence of a new pattern in the analog flow. Millman observes "there’s a huge interest in finding a way to incorporate parasitic data earlier in the design flow." And Filseth adds: "By accelerating the loop of schematic, layout, and extraction that generates the parasitic data, Helix may in fact provide a fast path for getting parasitics into the circuit designer’s hands quickly. It’s feasible to do a trial layout with Helix and your choice of routing tool while you are still experimenting with the schematic, so you can bring realistic parasitic data into the schematic and SPICE world."

This may turn out to be a vital aspect of the tool as frequencies increase and the relative importance of parasitic paths grows in analog and RF design. For now, the company has focused its efforts primarily on lower-frequency analog designs rather than taking on the science projects of the RF domain. But the growing intrusion of RF into SoCs may change all that, at it seems to be changing much else in the SoC design space.