10GBASE-T PHYs: when adding a port is a technical achievement

Moving from a single-port to a dual-port PHY doesn’t sound like a big project, particularly if it’s done by moving to a more advanced process. But the in the world of 10GBASE-T physical-layer chips, where the name of the game is achieving impossible data rates over twisted pairs, nothing can be as easy as it sounds. (For some background on the standard, see here.) Today’s introduction from Teranetics makes a good case study.

Teranetics introduced their single-chip PHY some time ago as a 130 nm CMOS design. Today’s dual-port part is a 65 nm CMOS design. That in itself sounds like it pretty much explains the design process, except perhaps for the signal-integrity checks. Smaller circuitry, so you can put two on one die.

But that would be a vast oversimplification of what actually happened, according to Teranetics VP marketing Kamal Dalmia. Moving a heavily-analog design from 130 to 65 nm involved significant new design work—not the least of which was a new data converter architecture—and constant attention to a parameter that might have been secondary in a single-port chip: power.

There is a not-so-obvious issue with power. The point of creating a multi-port PHY in the first place is to give network systems vendors higher density. But in many systems, density is limited by power dissipation, not by board area. So the power limits on each component in the system are becoming Draconian. To deliver the full value of greater density, the power has to go down sharply.

In the case of the PHY, Dalmia pointed out, that issue settles squarely on the data converters. You need a 10-bit, 800 Msample/s A/D and matching D/A on each of four twisted pairs attaching to the chip. All eight of these converters need to fit into a 1-Watt power budget. The resulting low-power converter design was sufficiently innovative to be an ISSCC paper in 2007.

One degree of design freedom the converter people had was to make trade-offs with the DSP section of the PHY. "In order to meet the power and bit-error-rate goals, the analog and DSP teams had to design together and produce a joint solution," Dalmia said. "We ended up with innovative architectures on both sides."

One of the innovations, as is happening across the industry as design teams produce precision analog circuits at 65 nm, is significant digital intervention in the data converters for trimming and correction. The PHY is gradually becoming a mostly-digital device, with 60 to 70 percent of the die area in gates, by Dalmia’s estimate.

The other major area of innovation was a very powerful LDPC (low-density parity check) decoder architecture that fit within the power budget of the PHY and could handle the enormous raw bit error rates one expects when trying to wring 10 Gbits/s out of copper. "The IEEE specifies the transmitter architecture in detail," Dalmia explained, "but leaves the field open for vendors to innovate on the receiver side. And it takes innovation: the decoder has to deal with incoming bit error rates on the order of one in one hundred, and produce corrected data with error rates millions of times better than that."

The impact of the dual-port chip at the systems level is significant. The first generation of 10 Gbit copper solutions came in at about $500 per port. By cutting the price of the PHY to under $100 per port, Dalmia thinks Teranetics is bringing the total cost to around $300 per port, while increasing density and reducing power. It was not simply a matter of porting a working design to a new geometry. But it could prove well worth the engineering investment.