Fujitsu launches USB 3.0 SATA bridge chip for PC external storage devices

Semiconductor vendors continue to sniff carefully at the USB 3.0 market. The opportunity has a flame-like attraction: it seems inevitable that the 3.0 standard, with its 5 Gbit/s transfer rate, will eventually replace the 480 Mbit/s 2.0 standard in most PC applications. But no one is sure about the rate of adoption. And it is clear that Intel will put a 3.0 host device in their core logic at some point in the future, and no one wants to still be recovering their investment on a host chip when that happens. To further complicate things, the 3.0 PHY, as a more demanding superset of the PCI Express gen 2 PHY, is a complex silicon design that requires a lot of development and verification time. So for the chip developer it’s a big bet on an uncertain table.

This has not prevented some companies from moving quickly. Fujitsu Microelectronics, for one, was an early designer of a 3.0 PHY in their proprietary 65 nm technology, claiming to be the first vendor to demonstrate interoperability, and demonstrating 200 MByte/s transfers at the Intel Developers’ Forum in Tokyo this May. But Fujitsu has not introduced a host controller. Instead, the company is cherry-picking applications on the device side of the USB cable.

Today they announced a prime example: a 3.0 to SATA bridge chip. The device is intended, obviously, as a connection between a USB 3.0 cable and a SATA external storage device. It incorporates an AES encryption engine—critical to many external-media applications—and Fujitsu claims the chip can support 300 MByte/s throughput with flow-through encryption/decryption.

Internally, the device includes USB 3.0 Revision 1.0 and 2.0 PHY and link-layer blocks. As have most design teams, Fujitsu chose to implement entirely separate 3.0 and 2.0 paths rather than to get clever about combining them, even though it doesn’t appear that there is any situation in which this chip would have to operate in both modes simultaneously. There is also a 3 Gbit/s SATA Gen2i PHY and link layer, of course.

Structurally, the chip includes an internal bus for data movement, the AES engine, and an unspecified 32-bit microprocessor core with attendant SRAM. The CPU’s job is primarily system control functions within the chip, such as initialization, dispatching tasks to the AES engine, and handling the intervention-required bits of the two link-layer protocols. The RAM is for code and data storage for the CPU rather than for buffering purposes, according to Fujitsu director of business development Davy Yoshida. The chip also includes an SPI port to an external serial Flash chip for boot-loading of code, and some general-purpose I/O pins for such things as status LEDs.

Power is going to be an issue in several respects for users of the device. The chip requires both 1.2V and 3.3V supplies, and consumes 550 mW typical. That means that a bus-powered interface with a local regulator to step the USB supply pin down to the required voltages would already be eating up most of the 900 mA allowed during operation, without passing any power on to the mass storage device. So interfaces using the chip will pretty well require an external power supply of some sort, probably furnished by the storage device. Further, according to Fujitsu, the chip’s USB I/O pins are not high-voltage tolerant, so they may require external protection circuitry to comply with the letter of the 3.0 specification about tolerating shorts to the power pin. One major bright spot for board-level designers, however, is that the chip has an internal spread-spectrum clock generator and so can operate with only a single external crystal.

Fujitsu is predicting that we will be seeing USB 3.0 in a variety of areas in addition to external storage. The company is looking hard at applications in both automotive infotainment and consumer electronics, for example. So don’t be surprised to see the company’s PHY surface in some additional bridge chips in the near future, and get included, perhaps in a more compact 40 nm form, in forthcoming consumer and automotive SoCs.