Marvell offers their ideas on design for low power

So much has been written in the last year about new tools and advanced techniques for low-power design that sometimes the fundamentals get lost in the mechanics. So it was refreshing to speak yesterday with Hongyi Chen, vice president of engineering at Marvell about how his design teams approach low-power CPU design.

The CPUs in question are Marvell’s ARM-9-like PJ1 and new Cortex-A8-like PJ4 processors. These are interesting designs in a number of respects, since they preserve legacy compatibility to the Intel XScale processors from which they descended, along with offering ARM V6 or V7 compatibility. Since Marvell has an ARM architecture license—in effect enabling them to do their own hardware implementations of an ARM instruction set architecture—the design team has many degrees of freedom in approaching a set of requirements.

But Marvell’s fabless model imposes some restrictions as well, Chen said. For one thing, the company has a policy of foundry-independence. Marvell currently uses both TSMC and UMC. This became an issue early on after Marvell purchased Intel’s XScale operation. Intel is famous for the degree of custom design that goes into their CPUs, and XScale was no exception. The Intel implementation employed self-timed logic in the execution units, for example. So one of Marvell’s early tasks in moving from XScale to PJ1 was to back out Intel’s custom circuitry and put in place synchronous logic that would pass inspection at TSMC.

The need to transport a design from one PDK to another without custom work has also informed Marvell’s approach to lowering power. The company uses pretty much the same tactics as everyone else—clock gating, power gating and the like. But Chen doesn’t get excited about techniques such as dynamic body bias that can make a design very process-specific. And he believes in doing the fundamental things first, before decorating an implementation with all sorts of active power management.

One of the most fundamental things is observing that lower voltages are better. Chen said the most basic power-management scheme Marvell uses is to design for greater than required speed in an LP process variant, and then simply turn down the clock and the voltage.

By using the LP process, Marvell automatically gets substantially lower leakage current from most cells. Then by choosing fast—as in 12-track—libraries, and by using the intensive design-for-speed techniques that are the company’s heritage on both the Power Architecture and XScale sides of the family, Marvell designers can produce a CPU core that runs significantly faster than the original requirements. A 600 MHz CPU might be designed for 800 MHz, for instance. That allows the designers to turn the operating voltage down significantly—thereby reducing both dynamic and leakage power substantially—and then recolse timing to meet the original lower spec. The power saved by reducing voltage more than compensates for any power consumed in designing for greater speed, and for the greater original voltage required by the LP process. Sometimes it’s the simply approaches that lay the best foundation.