Fujitsu launches RF CMOS at 65 nm

Levering their digital CMOS 65 nm process, Fujitsu announced this morning availability of PDKs and shuttle runs for a 65 nm RF CMOS process. Offering MIM and MOS capacitors, thick metal inductors, and an ft above 200 GHz, the company hopes to claim both stand-alone RF designs and, more importantly, SoC designs with integrated RF capability.

The process offering starts with a very-low-leakage triple-well baseline CMOS process with up to 12 metal layers. Fujitsu director of strategic marketing David Fung said that this process stands pretty much alone in the 65 nm community because of its conservative transistor design to deliver on low leakage, tight process controls to provide excellent device matching, and what Fujitsu believes is the lowest k-effective interconnect dielectric recipe in the industry, delivering an effective k of 2.2 to 2.3.

Onto this solid base Fujitsu has added the aforementioned passives, plus a great deal of modeling effort, a new tool for synthesizing inductors, and its own set of RF, analog, and digital libraries and memory compilers.

The modeling efforts have gone after the problems RF designers typically experience with CMOS designs, Fung said. Rather than try to hammer BSIM-4 models into some sort of usefulness, Fujitsu gave up and delivered Penn-State-Philips (PSP, see for instance here) models—physics-based models that use surface potential—for the basic transistors. For the same reason, the company developed its own model—called MOSVAR—for varactors, eliminating the errors inherent in BSIM-4 models of these critical devices. With both the transistors and varactors accurately modeled with accurate provision for digital noise, Fung maintained, it no longer needs to be normal to spin test chips three or more times to bring an RF PLL or tuner into spec.

The PDK includes not only the models, but also a tool called X-sigma for exploring the behavior of designs outside the normal 1-sigma range for process corners. This, coupled with a process control monitor tool that translates Fujitsu’s process control data into variability statistics in electrical parameters, permits the design team to explore yield issues over a much wider range of assumptions, according to Fung.

Fujitsu supplies P-cell libraries, and has chosen to develop its own digital libraries and memory compilers for the process, along with what Fung described as a rich assortment of analog and digital IP blocks. Presumably the latter include many blocks Fujitsu has developed internally for its own use, as well as synthesizable blocks from other sources. So the 65 nm process will join Fujitsu’s 90 nm RF CMOS process pretty much ready for full-scale design work. The PDKs for both processes are available now, as are shuttle slots.