Look in with envy: a strip-down report on Samsung's DDR3 65 nm DRAM

For SoC designers who struggle with getting a handful of high-speed serial I/Os to work simultaneously at 1 GHz, and who in the process give up a lot of die area because of conservative isolation rules and inefficiencies in the placement and routing tools, this is going to be painful, but have a look anyway.

In the second installment of EDN’s continuing series of IC strip-downs (and these guys mean the phrase quite literally) ChipWorks has analyzed the I/O circuitry inside Samsung’s K4B1G0846D-HCF8 1 Gbit DDR-3 DRAM. They did this the hard way: isolating the spine of the layout, and taking 76,000 SEM images of this area of the chip, which they stitched together on the floor and used to extract the circuitry. OK, that’s working hard. Just thinking about it is painful.

But for the SoC designer, it is also humbling a bit to look at the efficient use of space in the device, the fact that they get all those I/Os to operate at 1066 MHz, and that they do the trick with a 68 nm, 1-poly, 4-metal process. Take a look at a fascinating analysis, and appreciate how much of a gap there still is between what the EDA tools can do semiautomatically and what a big design team can do in full-custom.