ARM show new AMBA specs: think FPGAs and multicore

ARM this morning took the wraps off its plans for release of a new silicon interconnect specification: AMBA 4. The company intends to publicly describe AMBA 4 in two phases during this year. IP products implementing the specification will follow later in the year.

Director of marketing for fabrics Michael Dimelow explained that evolution in ARM’s markets has created requirements for the new spec. One set of driving forces is exemplified by ARM’s joint development with Xilinx. The point of that work is not to implement a small ARM core in an FPGA. That’s a solved problem. Rather, the work focuses on creating a framework for advanced SoCs—such as Internet-Protocol switch and packet-processor ICs—with substantial ARM CPUs, function-specific accelerators, and large embedded RAMs. Such chips are not small-scale microcontroller-like implementations, nor are they prototypes of ASIC designs. They are in themselves multicore SoCs that attempt to exploit the enormous potential bandwidth of the latest FPGAs.

ARM will address the issue of high-performance designs in FPGAs in phase 1 of the release. The phase will include three new variants of the AXI fabric specification. AXI4 is an evolutionary spec that mainly adds long-burst capability and quality-of-service support to the existing AXI interconnect fabric. Two completely new variants, however, are intended specifically for FPGAs. AXI4-Lite reduces the logic-element and interconnect footprint of AXI implementations in FPGAs, and AXI4-Stream adds streaming capability to the fabric, apparently to cope with peripherals or accelerators—like ARM’s own video engine—that produce a data stream rather than discrete bursts of packets.

The second set of driving forces comes from leading-edge cell-based SoC designs, not FPGAs. "We are seeing multicore architectures in which processors have local cache but share memory at higher levels in the hierarchy," Dimelow said. "Shared-memory multiprocessing has become common in servers, but now we are seeing it in embedded-computing SoCs."

This evolution is necessary to meet the computing requirements in many embedded applications. But shared-memory multiprocessing brings with it a host of challenges new to embedded computing: among them coherency, virtualization, and assured messaging. Data coherency across memory instances is necessary for systems to function correctly. Virtualization is necessary to get decent resource utilization, in SoCs just as much as in data centers. And intertask messaging presents its own set of problems, especially in virtualized systems where the order in which data items arrive at their ultimate destination can be hard to guarantee.

For each of these needs there are pure software solutions. But the software solutions become extremely complex, can have large memory footprints, and have a serious impact on system latencies. It’s better to move these mid-level services to hardware. And in fact some well-funded SoC projects have, for example, implemented proprietary hardware cache coherency. But such undertakings can be huge efforts, especially for the verification team.

For this reason phase 2 of the AMBA 4 spec release will introduce hardware support for coherency, virtualization, and message-ordering barriers. All of these should both relieve software developers of difficult, high-overhead tasks and standardize the way the issues are handled in AMBA-compliant systems. Product announcements later this year should offer off-the-shelf IP implementations of the new spec.

Dimelow said that he expects many AMBA users who are not involved either in FPGA implementations or high-end multicore designs to continue using AMBA 3, and that the two specifications will coexist probably for several years. But by attacking the problems in these new areas just as design teams are engaging with them, ARM hopes to begin an important conversation with system architects and to lay the foundations of standardization that will vastly simplify the problem of keeping operating software and middleware portable and reusable.