More from DAC: Can IP assembly ever be a real methodology for SoC design?

Some of the interesting action at DAC is always in the vendor-sponsored events in the surrounding hotels. One example this year was a panel, sponsored by memory IP vendor Sidense and recent Cadence acquisition ChipEstimate, on the future of IP integration methodology. The question before the panel was whether today’s practice of searching out, qualifying, and integrating third-party IP could ever have the rigor and consistency to be a methodology, or if it would always remain a case-by-case scramble.

Looking just at the question of formalizing the search for candidate IP, the panel set forth on a pessimistic note. Navraj Nandra, director of mixed-signal IP at Synopsys, warned that just establishing search criteria for mixed-signal IP could be a daunting task. "There are many criteria for even a familiar block like an A/D converter," he said. "As you drill deeper into the detail, the list of criteria is never complete."

Two panelists used similar metaphors in response to the question. Tensilica technology evangelist Steve Leibson commented that even the meaning of the phrase intellectual property could be fluid, and that establishing criteria for IP evaluation had no little measure of art in it. Sidense director of marketing Jim Lipman offered a gritty addition to the metaphor, saying that the whole area of IP requirements specification was quicksand. Even Adam Traidman, whose ChipEstimate Web tool has been helping designers find IP for some years now, was no more optimistic, warning that even within a range of similar IP it could prove impossible to specify on the front end criteria that would separate what you are actually looking for from similar items.

A second facet of the question was whether it was possible to standardize the IP evaluation and qualification processes so that they, at least, could be part of a defined methodology. The answer was again a pretty firm "no." Traidman said that even in large organizations with extensive IP evaluation teams, the evaluation process itself was ad-hoc, not standardized. "With all the variables, including the importance of the context in which the IP will be integrated, a single across-the-board approach is not possible," he said.

At this point Nandra emphasized the important role that test chips play in the evaluation process. He said that customer demand for test chips on evaluation boards has become so routine in Synopsys’s mixed-signal IP business that the company is now running a new test chip every three weeks through its foundry partners. "Customers want to see a test chip in their process. They want to see split lots, and a representative of a centered process. Just evaluating the test chips is getting complex enough that you could say test chips themselves are evolving a methodology," Nandra said. "It’s no longer enough for an IP vendor to tell you they have silicon. You want chips in hand that you can evaluate in your way."

This led to an audience question: is the model for IP evaluation shifting away from simply asking for silicon-proven blocks, and more toward something like a development partnership? Leibson responded that IP-based development has always been a partnership, and that cooperation between the vendor and the user is vital. Lipman added that increasingly, IP vendors were emphasizing customer service as a big part of their value proposition, and that he expected this shift to continue. To this Traidman commented that across the IP industry, revenues from service are growing as a portion of total revenue.

At this point a member of the audience interjected that when you evaluate a piece of critical IP, you aren’t doing a component evaluation—you are doing something very like a job interview, almost as if you were hiring the IP vendor’s engineers. Traidman agreed, saying later in the discussion that "the most valuable feedback you can get on a piece of IP is from another customer: what level of service do these guys really provide?"

The discussion moved in another interesting direction with a floor question about the integration process. "Can I get my IP vendors to work together on solving integration problems?" asked one listener. The questioner said that in ESD issues, for instance, it was very difficult to track down the source of a problem unless the IP vendors, who actually knew what was on the nets inside the blocks, would talk to each other.

To this Traidman replied that while we may or may not see IP vendors talking to each other, we are seeing some vendors doing much larger pieces of systems, which solves part of the problem. Lipman warned, though, that today cooperation between vendors would have to be customer-driven. He thought that perhaps we will see the emergence of intermediate-level subsystem integrators, who would bring together a diverse set of third-party IP into a specific subsystem, taking integration responsibility for everything in the subsystem.

A final topic from the floor was IP certification. Would it be possible for an independent third-party to certify correctness of, for example, a set of IP blocks working together? Traidman said that early attempts at this had failed, and that today responsibility for selecting and certifying IP had pretty much fallen back onto the broad shoulders of the foundries.

There were no formal conclusions, but from the discussion it appeared that if anything, IP selection and integration are moving in the opposite direction from becoming a formal methodology. They are increasingly evolving into a joint development between the IP vendors and the chip integrator. So maybe the correct question is, do we need to develop a methodology, or at least a set of best practices and a training program, for multi-party joint developments in which the focus is selecting and integrating IP?