Low power and FPGAs: a complex mix of issues

Actel Corp. announced a new line in the ProASIC3 family of low-power FPGAs today. The 3L family is intended to sit midway between the 350 MHz, 1.5V ProASIC3 line and the 150 MHz, 1.2V Igloo line. The 3L will provide 300 to 350 MHz operating speeds at 1.2V, according to Actel, offering nearly the system performance of the -3 line but with the power savings that come with lower operating voltage.

Behind the new line is an interesting story about what power management means in the FPGA world. Fundamentally, it’s different than low-power design for SoCs for one fundamental reason, according to Actel senior vice president Fares Mubarak: because when you are designing an FPGA you have no idea with what configuration it will be programmed, or what the use modes will be. So many of the most aggressive tools of SoC low-power design, such as dynamic voltage-frequency scaling, power gating, and even multi-threshold design are of limited use. They all depend on detailed knowledge of the RTL and the use models.

Instead, Mubarak says, the FPGA designer has just a few knobs to turn. There’s the choice of programming element—a natural comment for Actel, whose Flash programming cell can have considerably lower operating power than an SRAM-based cell. Then there’s the choice of process. Actel chooses to build the parts in 130 nm—in part, because that’s where they can get the Flash cells they need, but also because of the inherently low leakage. Beyond that, there are limited techniques for managing static and dynamic power, and these tools must be used with utmost diligence.

Successful control of static power demands highly accurate power simulation, according to Martin Mason, senior director of product marketing for the new line. Given an adequate set of tools, the process is one of combing repetitively through the design, net by net, looking for the highest remaining static currents, and swapping in high-threshold transistors wherever possible given the timing slacks. In larger cases, where a functional block doesn’t have to operate at full system speeds, creating a lower-voltage island is an additional alternative. But the voltage islands require close attention at the interfaces, to make sure there are no inadvertent current paths between voltage domains.

Dynamic power is a different issue. “The big culprit in FPGAs is the clocks,” Mubarak says. “Since you don’t know what load they will drive in a given user design, you can’t size them for minimum power.” So instead, Actel developed a power-optimizing place and route algorithm that clusters high-activity blocks of logic around the spines of the clock distribution network, and allows the blocks to be clock-gated with relative ease.

Another important issue for FPGA dynamic power is, perhaps surprisingly, inrush current. “Battery life is non-linear in current,” Mubarak observes. “So large current spikes reduce battery energy disproportionately. You must eliminate them.” That means not only preventing inrush current on power-up, but in all modes of the chip avoiding hazardous transition states that could result in spikes on the supply busses. Again, given the numerous operating, gated, and sleeping modes in which the devices can operate, and the unknowability of the user’s design, this is a non-trivial problem.

One of the most interesting points to emerge from this discussion goes back to Actel’s process choice: 130 nm. Clearly they are a biased source, since the company may be constrained to 130 nm until the 90 nm integrated-Flash processes mature further. But the company also makes a fairly compelling point that a particular set of design constraints—such as, we are designing an FPGA, not an ASIC—dictates the relative importance of static and dynamic power. And that balance may mean that the most advanced process operating at the lowest core voltage will not necessarily be the lowest-power process. It’s an analysis worth doing in detail.