TSMC announces Reference Flow 10

Hard on the heels of its iPDK and interoperable tool announcements, TSMC this morning unveiled Reference Flow 10, its latest recommendations for tool flows. The changes, as you’d expect, are incremental, but stake out some new technology territory for the giant foundry. There are three categories of additions to the flow.

The simplest of these is addition of a fourth track to accommodate Mentor Graphics’ Olympus SoC netlist-to-silicon flow. Mentor now joins Cadence, Magma, and Synopsys in having full flows recognized by the foundry.

More complex is TSMC’s addition of tools for early engagement with the 28 nm node. "Early customers are starting to look at 28 nm," said TSMC deputy director, design services marketing Tom Quan. "At this point the process is a moving target, but people are starting to need tools for test chips." That means design teams need tools that can handle some new kinds of design rules. Quan said that place-and-route vendors have had to rework their tools to deal with such issues as the direction-specific routing that will be necessary for the first time at 28 nm.

Additionally, Reference Flow 10 will show increased tension between users’ desire to stay with familiar corner-based analysis tools and the increasing value of the excess design margins they are spending by not moving to statistical tools. Much of the analysis in the new flow is still corner-based, including new multi-corner tools for clock-tree synthesis and concurrent power and timing optimization. But the flow also introduces stage-based on-chip variance analysis. Quan suggested that most teams would probably do multi-corner analysis on the full chip, and then go back over critical areas with statistical tools to whittle away excess margins. He feels that full-chip statistical analysis is still a ways away for most design teams.

One of the major sources of variation is the notoriously pattern-dependent variation in stress levels on individual transistor channels. TSMC apparently feels that it is no longer sufficient to attempt to minimize this variation with strict layout rules, and so is including a tool to analyze stress-induced variance effects at the circuit level. Power gets more attention at 28 as well, with a new pulsed-latch methodology and hierarchical power optimization tools added to the flow.

Perhaps the biggest change in the new flow is a first, tentative move toward support for system-in-package design. Quan said that it’s not even possible at this early stage to define one technology for SiP: the new flow will support both wire-bond and through-silicon via approaches to stacked packaging. "Customers are still on the fence about the value of SiP approaches," Quan said, "There are still some very significant problems. But it was time to start bringing in tools to support these efforts."

Accordingly, Reference Flow 10 will include four categories of new tools: thermal analysis tools for die stacks, electrical analysis tools for inter-die connections, physical design, and layout for 3D assemblies, and DRC/LVS tools for three-dimensional circuit assemblies. "Today most tools can only handle one die at a time," Quan said. "We are bringing in some tools that have been modified to handle more than one die, and some new tools as well." The SiP movement is still a long way from the ideal of a design flow that can handle layout and analysis in three dimensions with the same grace as a conventional single chip. But the new flow is taking a step in that direction.

TSMC will do a general release of the reference flow in Q3.