Beyond SoC and SiP: IMEC ponders 3-D circuit design

Buoyed by its ubiquitous application in cell phone handsets, multi-die packaging has become a serious alternative to advanced SoC design across a wide range of markets. The ability to reuse existing designs without integrating them into a larger SoC, to purchase known-good dice from other vendors rather than licensing IP and redesigning it, and the ability to use specialized processes when they are appropriate without increasing the footprint of the resulting chip are all very significant benefits.

Accordingly, as the use of multi-die packaging has grown, techniques have become more sophisticated. Early implementations with one small die stacked on top of one large die have evolved into stacks of a dozen or more layers. Wirebonding between the dice, although still probably the most common means of interconnecting the dice within the package, is slowly yielding to interconnect architectures that combine flip-chip techniques, redistribution layers, and around-the-edge contacts or through-die vias to make far denser, more reliable, and lower-impedance connections.

The Inter-University Microelectronics Consortium (IMEC) has been active for years in exploring these latter techniques, and has built up a repertoire of proven process steps for creating through-die vias, thinning wafers, aligning dice and multi-die bonding to fuse dense stacks of dice into multi-layer circuits. Now, the research consortium is looking forward to the next logical step: creating a tool flow that allows designers not merely to plan on stacking dice after the design is completed, but to genuinely design their circuits in three dimensions.

The distinction is an important one, according to IMEC vice president of business development Ludo Deferm. It is the difference between designing one chip at a time and then lashing them together, and designing a single three-dimensional structure in which placement and routing in the vertical direction are as natural as in the X-Y plane.

Deferm points out that in the future these capabilities are not just a matter of curiosity, but may become a matter of necessity. Increasing routing density, difficulties in scaling in the interconnect layers, growing problems with clock and power distribution, and soaring power densities for active circuits are all rapidly escalating issues. And all are addressed by a move from two to three dimensions.

But there are no tools today that make this transition natural. And there is little evidence that the majority of chip designers can be trained to make the transition from thinking of their floorplans in two dimensions and their implementations in text to thinking of the design as a three-dimensional entity. So IMEC is proposing a research program—for which they are seeking sponsor/partners—to develop a tool flow that will on the one hand allow designers to work in familiar metaphors, but on the other hand automatically generate a three-dimensional design.

The physical technology already exists within IMEC to implement the resulting designs. The organization has demonstrated through-die vias, surface contacts and even vertical waveguides for routing between dice in a three-dimensional structure. It has shown that these interconnect features can have sufficiently low impedance and high density that they can be treated, to the first order, in the same way as any on-die interconnect routes. And IMEC is in the process of developing an implementation of their software-defined radio architecture using the three-dimensional approach.

But the challenge now is to create a tool set that bridges conventional design experience to the new capabilities. This will require design planning tools; physical synthesis, place and route tools; and 3-D analysis tools, especially for new issues like thermal behavior. It’s not a minor challenge, but the reward will be quite literally to add a new dimension to IC design.