Innovative Silicon: a little company quietly upending the DRAM business

For years now, the DRAM industry has been an example of change by grinding evolution. Even in detail, DRAM structures have changed little, and then only when necessity would accept no alternative. Predictability and yield have been so prized that no benefit seemed attractive enough to justify discontinuous innovation.

But historically technologies that experience such success have grown increasingly vulnerable to sudden change from outside. And that may be happening to the traditional stacked- or trench-capacitor DRAM cell, right before our eyes. The source of the change could very well be a small but quite open company called Innovative Silicon, and the technology would be floating-body DRAM.

Some years ago, ISi introduced a DRAM cell, along with the accompanying technology necessary to build large DRAM arrays. The cell used the (to everyone else highly annoying) ability of the floating-body effect to store charge under the channel of an MOS SoI transistor–and thereby to change the transistor’s threshold voltage–as a storage element. In one stroke this eliminated the need for specialized processing steps to form a stack or trench capacitor, and it neatly tucked the storage element underneath the cell transistor. The design requires an SoI process, but for certain CPU and SoC vendors that isn’t a problem. Suddenly there was both a way forward that both circumvented the end-of-roadmap fears about conventional DRAM and provided a natural way to fabricate large DRAM arrays along with dense logic in a single, nearly standard process.

There were, as ISi admitted at the time, technical issues. The margin between the read currents from a cell set to zero and from a cell set to one was quite small, and the retention time was less than that of conventional DRAMs. Also, the write current when writing a zero was quite high, leading to relatively high system power for large arrays and potential neighbor-upset problems. But armed with a growing understanding of what actually goes on underneath the active channel region of an SoI MOSFET, the ISi R/D team set about to solve these problems.

A paper presented at IEDM last week indicates the degree to which they succeeded. The paper lists significant improvements in read-margin, speed, and power, without a fundamental change in cell architecture. But rather than being considered evolutionary work, in my opinion the paper deserves to be classed as a second piece of fundamental development in SoI device physics.

The improvements came, according to ISi co-founder Serguei Okhonin, not by simply tuning the known parameters of the cell, but by turning attention to a second active device—a buried NPN bipolar transistor—that had always been known, but considered just a nuisance parasitic path in the SoI MOSFET. This transistor is formed by the N+ depositions under the source and drain, acting as the emitter and collector, and separated by the P diffusion under the channel. In effect, the notorious floating body of the FET is the base of the NPN.

Most device models have regarded this intrinsic transistor as a pair of junctions or as a crummy transistor, in either case just another unwelcome bunch of leakage paths. But the ISi researchers realized that if they manipulated doping densities and profiles, then could intentionally build a pretty good bipolar transistor down there, in effect adding a second active device in parallel to the FET. The intrinsic NPN transistor would work with the FET, driving base current through the floating-body silicon just beneath the active channel region of the FET.

The paper reports that the bipolar transistor working in tandem with the FET generates significant additional current between the source and drain. In fact, according to Okhonin, the current through the bipolar device can be an order of magnitude higher than the Source-Drain current in the FET without the bipolar device operating. And this current is flowing through the previously-floating body area, directly altering the charge that influences the FET’s threshold.

So impact ionization from the base current generates charge in this floating-body region on a write-high, and the current sweeps the majority carriers out of the base on a write-low, increasing both stored charge—and hence margin–and write speed. The bipolar also reduces the voltage necessary to sweep out the floating body, reducing that source of power dissipation substantially.

These improvements in performance should make a lot of people sit up and take notice of floating-body memory. While they do not directly address one of the underlying issues in the technology—neighbor upset—the additional charge used in the new cell and the reduced write-zero current should help enormously.

As one might expect, ISi’s existing licensees, including AMD (presumably for embedded-memory applications) and Hynix (explicitly for bulk DRAM) have all licensed the new-generation technology. This could be the leading edge of the first major change for DRAM since the appearance of the stacked cylindrical capacitor wowed audiences with those Metropolis-like photomicrographs years ago.