Docea offers power and thermal analysis when you need it: at system level

Since the advent of CPF/UPF there are more and more tools to give you estimates of dynamic power dissipation based on a detailed RTL or netlist implementation, especially once you have declared your intent about voltage islands, clock gating, power gating, DVFS and threshold management. From this detailed power data you can use thermal-analysis tools to get a pretty good idea of steady-state thermal behavior of your die.

Unfortunately, that’s all a little too late. For years architects have understood that they have the most leverage over energy consumption—and hence, dynamic thermal behavior—at the earliest stages of architectural design. The further down the implementation flow you get, the less you can change power characteristics, even with drastic measures. What the world needs is a good power and thermal analysis tool that can work with the most abstract views of the design at the beginning, and then follow the design through to tape-out.

Experienced designers will object that such a tool exists: it’s called Excel. Engineers with enough experience can in fact build surprisingly accurate models of blocks using a spreadsheet approach, combine these models with estimates of activity based on use-cases or on application software profiles, and come up with remarkably accurate results. In some cases, these estimates have proved better than detailed power-analysis tool results that are based on the final design database and simulation value-change dumps (VCDs.)

But such good results depend on experienced users, a lot of design history with the IP in question, and some fine art. Now Docea Power is offering a tool that may deliver the same quality of power results, coupled with almost instant thermal analysis, without the need for that long history in power estimation.

The tool is called ACEplorer, based on the acronym ACE, for Abstract Concept of Energy, a term which itself remains pretty abstract. Version 1.1 was released earlier this month. Docea bills ACEplorer as an architectural power/thermal exploration tool—a way to get quick, accurate estimates of system dynamic power and thermal behavior during architectural modeling.

The concept apparently is to automate the work of building power and thermal models, and to borrow as much as possible from other sources. Docea CEO Ghislain Kaiser explained that ACEplorer worked in a number of phases. First, you construct an abstract power model using an XML formalism derived from SPIRIT’s IP-XACT format. Then you build activity files, either from VCD files or from timed flowchart input. All this is done through a GUI, so there are no proprietary languages to learn, and you don’t have to understand anything about XML.

ACEplorer can import the model data it needs directly from an IP-XACT file for an existing IP block. Or you can build up the model using the GUI, text descriptions in datasheets, spreadsheets, or an equation-based system. You represent your intent to manage power and voltage modes through state-machine descriptions, apparently in a format similar or identical to UPF. One important feature to mention here is that ACEplorer allows you to refine these models as you go along—as you decide more about voltage scaling, for instance, or develop RTL for a block and get better activity data and gate counts.

You build activity data and use-models similarly, by providing either timed flowcharts—early-on when you have only an abstract idea of system behavior–or VCD files later on when there is something to simulate in a virtual system modeler. There is apparently a utility that lets you match these VCD files to state diagrams, so the model can in effect learn just how much activity to expect in a given state. Thus the models can evolve along with the design. And they don’t all have to be at the same level of abstraction for the tool to work.

Separately, you can input thermal data from package models or build a SPICE-format RC network by hand to represent the thermal characteristics of the design. There are tools to assist in building these networks, and there is a model-checker to make sure that the network makes sense.

The actual analysis gets done in a proprietary electro-thermal simulation engine inside the tool. It produces dynamic power and temperature results, allowing not only RMS estimations of blocks, but locations of peak power and temperature, and permits evaluation of thermal runaway risk, power-integrity issues, and so on. The engine particularly shines in its approach to thermal analysis. Kaiser said that ACEplorer can produce a thermal simulation of a chip in about a tenth of a second with the same accuracy that would require a conventional finite-element-modeling thermal tool about four hours.

Docea says that you can establish automated links to the tools in your current flow through Python scripts, so you can easily refine the models as you go along. But it appears the huge initial benefit of ACEplorer will be for teams who are working in a relatively new area, where there’s not a lot of previous design experience with a particular silicon platform. By relying on data from IP-XACT models for IP you plan to import, and building new models interactively for blocks you plan to build from scratch, it sounds feasible to do real architectural exploration and get meaningful power and thermal data as you explore. That would give a team working on a brand-new project the kind of advantage that an experienced team working with a known platform only might have. And the savings in chip power, reliability, and schedule could be very significant. As with many new, complex tools, the remaining big question is the learning curve.