GHz I/O at 65nm and below: a Synopsys experience with PCI Express 2.0

Experience from advanced design teams doing multi-GHz I/O Phys in 65 and 45 nm processes is just beginning to diffuse out into the community. The initial impression is that these designs are very doable, but will require close attention to some new practices, and rigorous attention to some good old practices. A PCI Express 2.0 Phy announced today by the Synopsys mixed-signal IP group illustrates some of these points.

The IP, currently available for the Common Platform 65 nm process, provides a fully-compliant 5 Gbit/second PCI Express 2.0 link implemented in the standard G process, according to Synopsys group director Navraj Nandra. The group expects to tape-out a 40 nm TSMC version of the IP by December of this year, suggesting—even accepting the influence of market considerations on the schedule–just how non-trivial it is to move this class of design from one process node to another.

Beyond the familiar problems of making delicate, mixed-signal IP reusable, even with standard interfaces on both ends, there are purely functional issues that make PCI Express generation-2 IP challenging. Nandra categorizes these into four bins: jitter, losses, receiver sensitivity, and testability.

Jitter in 5 GHz SerDes and transceivers could be the subject of a book. But in short, Nandra says, there are a few outstanding noise sources to consider. The most serious from the point of view of reusable IP is intrusion of deterministic noise from outside sources into critical nodes, such as the PLL control voltage. Since an IP vendor can’t entirely control the placement and routing in the vicinity of its IP, the IP design team has to conceive and design to a worst-feasible-case scenario. This means strict attention to guard rings, placement, and node impedances within all the critical analog nets of the design. As an example, Nandra cited extensive use of cascode structures to make sure critical nodes were high-impedance.

Unfortunately, simulation—particularly of substrate noise—is not sufficient to evaluate noise immunity in these designs. Nandra says that a key tool in evaluating the external-noise sensitivity of the PCI block was a test chip that included the IP along with substrate and supply noise generators. Another critical element in noise evaluation was a built-in test tool—nearly the equivalent of a digital scope. More on that later.

By 65 nm, and certainly by 40 nm, random noise is also a significant issue in the jitter budget. This the team fought by making signal-path devices as large as possible, and—in a tip of the hat to the ancient history of amplifier design—by using chopper-stabilized circuits to shift random noise into higher frequency bands where it can’t cause so much trouble. "There is a trade-off between noise sensitivity, current, speed, and area," Nandra observes. "When you are designing for reuse, you have to make that trade-off in a way that leaves your customer with the largest possible jitter budget." Nandra says that the result of all the work on noise immunity means that under pretty worst-case conditions the block can still maintain about 1 pm RMS jitter.

Signal losses in the intended application are another area the Synopsys team addressed. Nandra said that at 5 Gbits/s, it’s not unusual to lose 15 dB on a typical FR-4 trace. The PCI Express gen-2 spec provides for this by specifying up to 6 dB of pre-emphasis, which the Synopsys IP implements. The IP designers went a bit further, providing additional programmable launch amplitude.

Similarly, receiver sensitivity becomes an important issue. The Synopsys team decided to add an additional programmable gain stage to the receiver circuit to recover low-amplitude signals that have been mostly eaten by the circuit board. Both the transmit and receive-side programmable functions are to be tuned using circuitry in the receive-path that generates the data for masked eye diagrams and extracts them through the JTAG port. Thus users can set pre-emphasis, launch amplitude, and sensitivity in a particular environment by observing the signal inside the receiver chain, not at some loosely-coupled test point.

Finally, there is the interesting issue not of the rest of the chip interfering with the PCI Express block, but of PCI Express interfering with the rest of the chip. "We are starting to see PCI Express used in wireless SoCs that have on-chip radios," Nandra says. "Accordingly, we have put spread-spectrum circuitry in the transmit PLL and clock/data-recovery circuits that can be switched on to keep harmonics of the PCI frequencies away from radio receivers."

The pattern seems to be one of intense focus on noise, using large signal transistors wherever possible, and using the high speed and huge transistor budget of the advanced processes to create programmable work-arounds for integration problems. These techniques, Synopsys demonstrates, not only make 5 GHz design possible, but make design for reuse feasible in at least 65 nm.