Analog IP, meet 65 nm CMOS: early adventures from mixed-signal IP vendor S3

The end of scaling for analog and mixed-signal CMOS intellectual property has been, like Mark Twain’s death, prematurely reported—perhaps the former rather more often than the latter. It has always seemed intuitively obvious that at some nearby process node, fragile, cranky, semi-magical analog is just not going to work any more. But the announcement by S3 last week of a library of mixed-signal IP for TSMC’s 65 nm LP processes suggests that the reports are still premature.

Reassuringly, the announcement is based on characterized silicon, not on promising simulations or the approach of a particularly expensive tape-out. The IP blocks characterized at 65 nm so far include 10-bit ADCs at 30 and 40 Msamples, an 11-bit, 160 Msample sigma-delta ADC and a PLL.

So what is analog design going to be like at 65 nm? A lot like 90 nm, according to S3’s director of marketing Bob Tait. He says that a methodology strong enough to produce good 90 nm designs will continue to work at 65, with the only major difference being the increased level of activity around design-for-manufacture in the design flow.

But at the same time, Tait admits there are circuits that probably won’t port successfully to 65 nm. “There’s less and less headroom,” he says. “You have to understand the limitations of the process, and of your tools.”

This may cause some rethinking as consumer wireless vendors—S3’s primary target for the IP—make the move to 65 nm. For example, there is a tendency to look at specifications like 802.11g wireless LAN or 802.16 WiMax and think that because of greater noise sensitivity and, in the latter case, far greater channel bandwidth, ADCs with greater precision will be necessary. But ADCs with greater stated precision may not be available at a reasonable cost in real estate. So architects may have to rethink their approach to the signal chain.

“We’ve been working with customers’ system architects on this,” Tait said. “You can actually achieve a 66-67 dB spurious-free dynamic range with a 65 nm ADC. And if you manage the noise budget across the whole signal chain, that can be enough to meet system requirements. But it takes planning ahead, finding ways to use the blocks you can actually build.”

The bottom line here may be that even though we are going to see familiar mixed-signal libraries available at 65 nm, we are also seeing the leading edge of a long-predicted phenomenon: changes in system architecture that directly respond to the limitations of the process in implementing signal chains. Right now the alterations may be incremental, but by 45 nm they may be profound.