Heard at SPIE: Applied Materials panel looks for the future of lithography

The lithography for IC manufacturing is at perhaps the most confusing crossroads it has even encountered. It is clear that the current state of the craft—single-patterning immersion optical printing at 193 nm—cannot take us much further. But it’s not clear what will come next.

Addressing that question, Applied Materials sponsored a panel discussion during their technical seminar at SPIE this week. Panelists were Grant Willson of the University of Texas, Burn Lin of TSMC, Jongwook Kye of AMD, Steve Radigan of SanDisk, and Milind Weling of Cadence. These luminaries put their heads together against a simple query: what happens in 2016?

The problem, of course, is that the current technology may be able to get us through the 32 nm logic node, but not much further. Several alternatives might take us to 22 nm and beyond, but all of them are intertwined strands of lithographic technology, patterning technology, and EDA technology, no longer really separable into independent issues.

We can identify the braids, even if we can’t tease out the strands. One possibility is to continue the development of double-patterning with existing 193 nm immersion lithography, and the considerable help we might get from restrictive design rules and source-mask optimization tools. Another path is to rely on as yet far too slow multi-beam direct-write electron-beam printers. A third—and now perhaps fading—approach is the much-touted EUV. And finally there is a technology already in use in some specific applications but not widely appreciated: mechanical imprint lithography. Each has promise, but each has potentially disabling problems.

Willson, who has done research in imprint technology and is associated with Molecular Imprints, argued briefly but forcefully for that technology as an alternative. He pointed out that today, an imprint lithography station costs about a tenth of what an advanced scanner costs. At that difference, and given the angst in the industry over the rising costs of fabs and the consequent consolidation of foundry capacity into a few wealthy hands, he argued, doesn’t it make sense to invest in solving the issues with nano-imprint as a production technology for logic? That question stood unanswered by the rest of the panelists.

TSMC’s Lin backed another favorite horse, given the money that the giant foundry is sinking into multiple-beam e-beam systems research. He put together a matrix comparison of multiple-beam, double-patterning, and EUV technologies, rating them on finished wafer cost, mask cost, status of development, and required investment. After this comparison of costs and benefits, Lin concluded that the industry should pursue two paths. First, it should invest in e-beam development. Second, as an interim, it should invest in bringing down the cost of double-patterning.

For this last point, Lin had a two-stage (pun perhaps intended) proposal. First, he said, we need to develop a resist that could work well enough to reduce the cost of double-patterning to the cost of double-exposure. Then he proposed developing a dual-stage scanner that could make both exposures simultaneously. This would significantly reduce the time the wafer spends at the litho step, and hence the cost of the wafer.

AMD’s Kye came at an endorsement of double-patterning from a different angle. He also suggested two steps, but using existing equipment. First, he said, we need to pursue the litho-litho-etch variant of double-patterning, which eliminates a redundant etch step between the two exposures. "The litho-etch-litho-etch approach is just too expensive," Kye said. "We can’t afford it."

Then, he added, we need to make chip designs more amenable to double-patterning by, in effect, developing design-for-double-patterning tools: a design flow that creates easily-splittable patterns. Kye observed that, for example, the litho-litho-etch process can freeze a line from the first litho step and preserve it through the second litho step, but it can’t similarly freeze a space. What we need, he said, are gridded design rules to simplify the patterns we are trying to create, and then new decomposition algorithms to split the patterns between the two consecutive litho steps.

To some degree Kye’s argument echoed an earlier presentation by Applied Materials, which favors yet another form of double-patterning, self-aligned double patterning (some discussion here) in which side-wall spacers actually form the pattern. This approach too, it turns out, is heavily dependent on EDA tools and highly-restrictive rules to produce patterns suitable for splitting.

SanDisk’s Radigan, coming from the very different culture of Flash memory manufacturing, had yet another view. "Double-patterning is a stop-gap," he said, "which is becoming mainstream because there are no viable alternatives." But Radigan predicted growing issues of cost and complexity as we try to extend double-patterning beyond the 32 nm node. He similarly questioned the real mask costs for imprint lithography in practice, and the real schedule for EUV. Then he pointed to e-beam technology. "It is mature, and in fact it is already used in each of the process flows we are looking at. It’s just not yet showing the throughput we need for production." So why not, he asked, focus on raising the throughput of multi-beam e-beam systems?

Weling concluded the discussion with an EDA perspective. He began by observing that in the last six months, more questions seem to have been raised about EUV, challenging it’s presumptive role as the successor to immersion. "Last year the question on EUV was when. Now it is if," he said.

Without EUV, "at 32 and 22 nm it is the software that is changing, not NA or λ," he said. But today, Weling worried, each user of double-patterning has taken a different approach, each requiring a different design-for-manufacturing solution. That doesn’t make a viable problem for the EDA industry. Weling encouraged lithographers to look at double-patterning not just as a lithographic technology, but as a software process that begins clear back at the netlist level of chip design, with optimizations and restrictions that would influence the design. With that deep influence on the design flow, he suggested, EDA could produce designs that could be split for double-patterning with good results.

If there was a consensus in all that, it seems to have been that some form of double-patterning is of necessity the next big thing after 193 nm immersion and the darling of this year’s SPIE, source-mask optimization. But Weling has a good point that the EDA industry can’t support a half-dozen entirely different approaches to the technique, and the technique can’t succeed outside the Flash/DRAM space without the EDA industry. Another potentially very important point is that there seems to be a growing willingness to accept multi-beam e-beam lithography as a potential production tool to take the place apparently being vacated by EUV. That all makes for quite a crossroads.