SoI Industry Consortium stalks the Green Thing

In these days when only government spending seems to drive the economy, everyone is lining up to be under one of those government spigots. This is a little tricky for the semiconductor industry, since it’s hard to make a case for a fabless semi company being essential to bailing out Morgan Stanley, rebuilding our highway infrastructure, or checking the spread of swine flu. But there is one area in which chips and foundries can claim some home turf: energy-saving.

Accordingly, just about half of new marketing programs have the word "green"—often capitalized—somewhere in the first paragraph. Often this is little more than spurious: an amplified echo of last year’s key phrase, "low power." But in some cases, the appeal to greenness makes sense, even without adding chlorophyll to the package epoxy.

One of those is a new initiative by the Silicon-on-Insulator Industry Consortium: Simply Greener. Part of the point of course is to hitch SoI to the Green bandwagon. But there’s content in there too: one of the significant advantages of SoI is in fact its ability to deliver a better speed-power product on a given project than a similar-geometry bulk CMOS design. This fact might have been obscured by some of the more prominent press stories about SoI—AMD’s travails and heat problems with industry-leading game consoles to name a couple. But it’s none the less true.

A point the SoI folks want to make clearly is that you can use that speed-power-product advantage to save significant power at the same speed. To underline that, a recent presentation gives examples of benchmarks done by ARM and IBM, doing side-by-side designs of specific blocks in SoI and bulk CMOS. In ARM’s case, a 45 nm datapath design, the SoI version achieved almost a factor of three reduction in leakage and about a 20 percent reduction in dynamic power. IBM’s example was less apples-to-apples: a full-chip migration from 65 nm bulk to 45 nm SoI, resulting in about a 1/3 reduction in power and a 50 percent speed-up. In these instances, the choice of SoI instead of bulk process appears to be making more difference than the use of aggressive power management.

The mechanism for the efficiency gain appears to be simple—probably simpler than it actually is. Because SoI builds its transistors directly over a buried insulating layer, the parasitic capacitances from the source, drain, and channel are hugely less than in a bulk wafer. By reducing these capacitances, the SoI transistor can operate with lower drive current, and hence can be smaller and/or can have a higher threshold voltage. Thus both leakage and dynamic currents can be smaller at the same performance.

A second point the SoI Consortium want to emphasize is that SoI is available as an off-the-shelf foundry process, not just as a full-custom technology. "There’s a wide range of regular users now," insisted Consortium executive director Horacio Mendez. "Almost everything IBM is building at 45 nm is in SoI, as are all of Freescale’s latest networking chips. Casio is using the technology at extremely low power levels for watches, and some vendors are applying the technology in automotive applications." Foundry service is available from IBM and Chartered Semiconductor, among others.

Not only is SoI a viable option for ordinary design teams, but it has a roadmap, the organization claims. Processes are available in 65 and 45 nm, and both 32 and 22 are on the drawing boards. The main take-away the consortium would like to leave you with is that SoI brings built-in power-savings, and it is mainstream. That’s a point that deserves some discussion, even from teams that are already tooled-up for bulk CMOS.