How to design a 40-billion-transistor SoC (and live to tell the tale)

Keynoting the Mentor Graphics U2U meeting in Santa Clara this morning, Mentor chairman and CEO Wally Rhines delivered one of his signature tightly-reasoned essays on the future of IC design and what we might do about it. The topic was, roughly, SoC design in 2018.

Rhines started with his frequent observation that Moore’s Law is actually not a law, but more of an observation. And at that, it is a particular case of a learning curve: that nearly universal law of human endeavor that mandates a linear relationship between the log of unit cost and the log of cumulative volume. Extrapolating from the days of vacuum tubes through the ups and downs of recent years and into the dark sub-nanometer future, Rhines pegged the headline chips of 2018 at 40 billion transistors each.

But then the executive pointed out that the time interval from introduction to production-worthy use for a major new EDA technology has always been about eight years. So in all likelihood, the EDA tools that produce those 40 billion transistors will have to use technology that is just coming to market today. Rhines took a quick stroll down the chip design flow to show how productivity improvements at each stage could make this possible.

His first stop was the system level, where Rhines predicted a shift to transaction-level design, using models that the users can create for themselves. This work, he suggested could be done in any of a number of environments that are already in limited use for system modeling and synthesis in the software world, including UML, SysUML, and the automotive industry’s autoSAR.

For verification, Rhines said we would need at least a three order-of-magnitude increase in productivity. Then he listed steps that could get us there: hardware emulation, the ploy of simply eliminating redundant simulation runs during verification, the use of transactional test benches, and learning to blend simulation, emulation, and formal verification into a single approach. Taken together, these steps, all of which would rest on groundwork that exists today, could improve verification productivity by anywhere from three orders of magnitude to 14, Rhines estimated.

Turning to physical design, Rhines observed that about every two and a half years the problems of placement, routing, and analysis become sufficiently more complex that some start-up comes along and rewrites the rules. This happened most recently, he suggested, with techniques for doing simultaneous multi-corner, multi-mode analyses, and with the use of threading to adapt analysis tools to small numbers of cores. The next step, Rhines said, would be a tight integration of routing code with design-rule and design-for-manufacturing analyses, eliminating the need for physical-design respins to accommodate DRC ECOs. In addition, this integrated router will be parallelized—as has already been done with board-level routers—providing nearly-linear performance scaling on up to dozens of CPU cores.

Finally, Rhines addressed the submerged nine-tenths of the development berg: software development. By applying existing ideas—design re-use, software design automation, and open-standard packages for operating systems and middleware—Rhines said, the now mostly hand-crafted world of embedded software development could achieve the necessary gains in productivity to keep it from being a game-ending problem.

With that, Rhines rested his case, having shown that in every major stage of the development cycle it was possible to use today’s new ideas to achieve a factor of a thousand improvement in productivity. If you were keeping score, you might note that he did not mention synthesis, quietly leaving no additional step in between transaction-level system modeling and verification. That ellipsis might very well point us to a Mentor strategy aimed at compensating for their relative absence from today’s RTL synthesis market.