Cadence grapples with IC power estimation and analysis

In a series of somewhat-related announcements earlier this week, Cadence rolled out several new capabilities aimed at managing and modeling power in chip design. One is an architecture-level power estimation capability, one a dynamic power analysis tool, and one is actually a cluster of new capabilities brought into the Encounter sign-off analysis system.

Starting at the beginning of the flow, there is Incyte: basically a rebranding of the quite effective architectural estimation tool from ChipEstimate, which Cadence recently acquired. What is new here is that Cadence is integrating the ChipEstimate tool into their product line as the front end of the low-power design flow. The first major step in this process seems to be that the ChipEstimate tool, along with its previous capabilities for exploring the architectural space for power-management strategies, can now capture a particular set of architectural decisions automatically in a CPF file. While this may sound like a minor step, it is actually a big break for chip architects. CPF has been a headache specifically because creating the file has been a purely manual process, requiring Tcl entry, manual table checking and, in reality, waiting for the physical verification team to find the subtle errors in the file. Automatic CPF generation, if its limitations are not too severe, should go a long way toward eliminating this bottleneck.

The second new offering is from an entirely different direction: Cadence’s Palladium hardware emulation system. The company has created a dynamic power analysis package for Palladium, allowing Palladium users to load application software along with the RTL design onto the emulation system and execute actual code—millions of cycles worth—in a reasonable time, all the while estimating peak and average power consumption. The tool has obvious value for early power estimation, evaluation of soft IP, and other such tasks in power-critical designs. This becomes particularly important as the use of programmable functional blocks with advanced power management increases, as advanced power management makes the actual power consumption of the circuit strongly dependent on the system and application software.

But the tool has its limitations as well. Because it is a pre-placement tool, the analysis cannot estimate the critical issues of transient local power consumption or its dire consequence, local heating—it doesn’t know what local means yet. This would appear to limit the predictive ability of the tool to block- or chip-level averages, which may or may not be useful in advanced processes, since they can’t be trusted to even mark the presence of worst-case local power or thermal problems. Also, since the tool doesn’t track leakage, it will be of limited use in assessing the actual power, heat, and energy situation in modern processes with high leakage currents, where power management is the ability to juggle static and dynamic power, not the ability to optimize one at the expense of the other. Still, using .lib files, the RTL source, and the product software as inputs, and coupling into CPF, the dynamic power tool should be very valuable as it stands.

The final piece of this cluster of announcements is a power-integrity and sign-off power analysis tool that fits into the Encounter framework. There don’t appear to be any new checks or analyses here—power grid integrity, decap and power switch optimization, IR-drop analysis and such are all things that are now covered by point tools. What is new, and important, is that these point tasks are now integrated, as Encounter Power System, into the Encounter framework, where they interact directly with Encounter Timing System. Thus vital interactions such as the timing impact of IR drop in the power grid or noise on the power pins can happen automatically within one framework. It should no longer be necessary to laboriously port the output of a bunch of point tools into the inputs of Timing System. The result, according to Cadence, is improved accuracy for the analysis tools and significantly reduced time-to-market.

Slowly but surely we are untangling the tangled web we wove by undertaking aggressive power management in the first place.