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A cold and changing world for silicon IP

December 28, 2009

At this point in the year it is customary to sit back, ponder the year’s events, and try to divine some trends: some patterns in the flocks of news releases, meeting notes, and conversations that now gather, take wing in the chill air, and turn South—out of the summer country of short-term memory and toward the cold land of yesterday. To be fair it is not from any improved perspective that we work this augury, but merely from the cold fact that in this bridging week there is so little news.

It need not be said, but to 2009: good riddance. This year has seen many fine engineers take up consulting. It has watched promising companies scratch for revenue, find none, and quietly begin shopping their IP around as the precious capital drips away.

But these hard economic facts may have obscured an entirely separate pattern: a technological shift in the IP industry. The visible surface of this shift has been consolidation. Beneath that level moves an even more pervasive change: increasing integration is pushing the need for system-level expertise further up the supply chain. SoC vendors have become systems vendors. And of necessity, IP vendors are having to assume responsibility for complete functional subsystems.

The pattern has been evident for some time. Application-independent IP blocks such as DRAM interfaces are now sold as complete functioning subsystems, not as sets of parts from an IP catalog. ARC and Tensilica, the two major configurable processor core vendors, have long since shifted from trying to sell CPU core kits to providing complete hardware/software/verification packages for specific functions, such as handset audio processing. The configurable processor core is still in there, but it’s almost incidental to the product. In fact the entire applications plane of an Android handset appears on its way to becoming a single piece of IP.

What does this mean for IP vendors? Fell words. Unless you are offering a full subsystem or an analog/mixed-signal function not available elsewhere, your customers will be other IP vendors, not SoC designers. And your margins will be nil. If you do offer a full subsystem, the cost of admission will be a fully-functional reference design in the target process—forget FPGA implementations—with all the software, including some differentiating functionality, a full verification suite, all necessary industry certifications, and the design support necessary to ensure your customer will succeed in tweaking and integrating your subsystem.

If this sounds beyond your means, there is a simple conclusion: you are too small to stay in the silicon IP game by yourself. Your business is equivalent to offering quad NAND gates to an industry that is designing with microprocessors. Not impossible—there are still vendors selling discrete logic today—but not exactly a business plan you would want to present to investors.

So welcome to 2010. If we are lucky, the current supply-chain mini-bubble will relax gracefully instead of bursting, leaving behind slow, excruciatingly margin-conscious growth punctuated by a few stand-out products areas. As the storm clears, we will look to the skies and see just how much of the IP business we knew has migrated to a new model, and how much has flown South forever.

Posted by Ron Wilson on December 28, 2009 | Comments (9)

January 12, 2010
In response to: A cold and changing world for silicon IP
DannyBoy commented:

How can I find more information related to this post? Its very interesting and I think this will benefit others after reading through the provided material. Thank you and keep up the good work!


January 2, 2010
In response to: A cold and changing world for silicon IP
H@UK commented:

What is also an interesting question is at what point the ability of Intel & ARM to provide a full CPU + interconnect 'backbone' + security IP + key connectivity blocks (HDMI/PCIe...) plus the required associated linux infrastructure will trigger small quality teams to put together real SoCs (remember the S stands for 'system' - increasingly forgotten) with a low level of investment (time and money]. We should not think that mask costs in 55nm or even 40nm (or 32/28nm..) are the most significant costs for an SoC - it is engineering effort + time-to-market. I would see this as ideal for either; - new start-ups owning some novel IP 'widget' and looking to get real revenue stream and significant share of their chosen market by exploiting their IP. - large tier1 brand names wanting to add value by properly defining their systems from the top down - sw -> system -> implementation. (a la Apple). At this point ARM has some difficult questions to ask itself w.r.t. its relationship with it's traditional customers i.e. the large resident providors (IDMs & fabless) of devices to the consumer market; and Intel has similar discussions with it's own internal teams... The barriers to entry for traditional SoCs continue to fall - interesting times ahead.


December 30, 2009
In response to: A cold and changing world for silicon IP
Rich Wawrzyniak at Semico Research commented:

Ron, As process technology improves over time, the complexity of the silicon possible also increases. Your article points out that this trend towards higher levels of complexity and integration also extends to the 3rd Party Semiconductor IP market. As the number of discrete IP blocks on an ?average? SoC moves beyond ~50 and quickly approaches ~100, managing all these discrete blocks becomes a very large task in itself. The amount of granularity available to the SoC designer has been maximized but at an increasing penalty of more interoperability issues, lengthening design time, resource allocation and design costs. As you correctly point out, the growing use of discrete IP blocks assembled into larger Sub-systems, which also includes some of the applications software, is a very efficient way of addressing these issues without reducing the range of choices available to the SoC designer. More and more IP companies are referring to their products as Sub-systems and going forward, the IP Sub-system will become a product category in its own right. I think you are providing a great service to the SoC and IP design communities in your illumination of this topic and the issues related to it. As you are able, please continue to write articles about this subject.


December 30, 2009
In response to: A cold and changing world for silicon IP
garydpdx commented:

Along these lines, the global great recession has slowed investment in efforts to support and utilize IP-XACT as an IP transport mechanism when automating CAD flows. The standard did make it to the finish line, with the SPIRIT Consortium merging into Accellera. But we're awaiting word on when work on IEEE standardization will commence. The last major publications were by Magillem in 2Q, 2009 on work done on behalf of OCP-IP, and a conference paper at IP 2008 by Montreal's Ecole Polytechnique. (Nothing at this year's IP-ESC 2009, or did I overlook something?)


December 30, 2009
In response to: A cold and changing world for silicon IP
Phil Casini - Advance Tech Marketing commented:

Ron, You are right on point with this article. You have summed up the dynamics quite well. I would like to add that not only is there consolidation happening, but also polarization. The deals Virage made with AMD and NXP are leading indicators of what chip companies now want, strategic alliances with stable IP suppliers who can offer them a portfolio of IP. They dont want to deal with multiple IP vendors. IP vendors who do not amass portfolios and/or don't add strategic value are going to die. The other point you hit on which I believe is a very valuable observation is the notion of subsystems. Given the compleoxity levels we have reached, the economics are now far more in favor of integrating larger blocks that solve more of a system level challenge because they have a ripple savings effect on development costs and time to market. Subsystems touch virtually all disciplines, from arcehicture and chip design, to verification, software development, and even bring up and debug. Subsystem utilization then allows the savings to compound through the development project. You just don't get the same effect from using conventional IP blocks.


December 30, 2009
In response to: A cold and changing world for silicon IP
Jüri Põldre commented:

Shift from single powerful CPU into multi-core system brings along need to provide this functionality to system integrator. It is not uncommon now to have design kits where register defs are not available and you talk through SW API. Since our feet are still firmly in single CPU enviroment all major DEVKIT/SOC players have to tweak existing sw to add support for this concurrent HW through non-concurrent API thus keeping engineers in cosy known enviroment. All too very often this requires additional tweaking at crucial points to keep flow fluent. Long story cut short IMHO we are currently at a phase where distinguishing selection feature between SOC providers is knowledge about specific sw switches to pull@correct time for making most out of underlying hw. Hopefully we will have some unified understanding & capable platform of parallel programming (not threads) in some sunny day :-)


December 29, 2009
In response to: A cold and changing world for silicon IP
IP commented:

High Value Change as Technology Industry Dynamics.


December 29, 2009
In response to: A cold and changing world for silicon IP
Dieter ERNST commented:

Thanks for an excellent analysis of the dramatic changes in Silicon IP. This raises the question: As Tensilica and ARC are providing complete hardware/software/verification packages for specific functions, such as handset audio processing, how does that affect their innovation offshoring strategies, and what R&D jobs are they now conducting in India and China?


December 28, 2009
In response to: A cold and changing world for silicon IP
shawnkempf commented:

Healthy samples are giving free winter samples for a limited time at www.bit.ly/5dxDmw

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