Start-up Gemini joins parallel SPICE club

Capacity and speed for analog simulation have become pain points in the design process for a variety of reasons. Analog component counts in SoCs are growing. Models and nets are getting complex, especially when designers add in interconnect and substrate parasitics, or attempt to model the things that happen to a transistor with a very short channel. Increasing variations force either an explosion in corners or Monte-Carlo proliferation of runs. Adding large numbers of digital nets to analog signal paths in an attempt to compensate for the shortcomings of those little transistors makes the simulation problem even worse. All in all, the situation has gone from an annoyance to the point where whole classes of analog devices no longer converge with traditional SPICE.

Not surprisingly, acute pain brings new ventures. Recently we discussed Infinisim, which has attacked the problem with a unique approach to partitioning the circuits and selecting matrix solvers on the fly. Monday another start-up with an all-star pedigree, Gemini Design Technology, took the wraps off of their idea: a thoroughgoing attempt to multithread the two major bottlenecks in SPICE.

Gemini’s executive chairman—and chief cheerleader—is industry legend Jim Solomon. President is Baolin Yang, an R/D guy formerly with Cadence. As you would expect if you enjoy comparative anatomy of analog simulators, the technical team includes, in addition to Yang, a partitioning and database guy, Xiaodong Zhang, and a modeling guy, John Qian both also with Cadence background as well as other credentials. So this is not somebody’s thesis project out gold-digging.

Gemini’s concept, as outlined by Solomon, is that if you start with a clean sheet of paper and what is known today about model evaluation and matrix solving, you could create new multithreaded algorithms that would produce the same results as existing SPICE, but would be both faster on a single CPU and scalable to multicore systems using four or more cores. That is the thumbnail of what the team has done, and Gemini claims to be two to ten times faster than tuned SPICE or threaded SPICE approaches with no compromise in accuracy.

These results come, according to vice president of marketing and sales Kent Jaeger, from several major efforts. One was developing the new multithreaded algorithms for both model evaluation and matrix solving. Another was creating a front-end partitioning tool and a master database from which the analytical codes could work. And there was development of a dynamic thread manager that determines the optimum task dispatch for a given design dataset and number of CPU cores.

The team stayed with strictly industry-standard input, model, and output formats, so the tool should in principle be a drop-in replacement for existing analog simulation without altering methodologies. The take-away, according to Gemini, is that you can drop a new simulator into your current methodology and get the same accuracy as before, but with the capacity and speed you’d expect from fastMOS. That circumvents the whole problem of creating a special view of the netlist for fastMOS and then fudging the results with comparison against shorter SPICE runs to correct fastMOS’s errors.

The proof will be in the proverbial pudding, and as you would expect Gemini has a collection of benchmark results from actual circuits, showing speed increases over earlier accelerated SPICE codes of from about four times to more than two orders of magnitude. One nearly half-million-element oscillator analyzed post-layout would not converge at all on another product, but ran in a mere 11 days in a 16-thread configuration.

Clearly your results may vary, depending on your netlist and your models. Equally clearly, parallelized analog simulators that take different approaches—such as Gemini’s and Infinisim’s—may show quite different results on the same problems. But from the data so far, it appears that analog design teams working at advanced geometries must take the time to evaluate this new generation of simulation engines.