FPGAs aren't gone yet—or even slowing down. But ...

Just to add some balance to my previous posting about the future of FPGAs, I thought I should introduce a little corrective reality. In a recent conversation with Pratul Shroff, president and CEO of design house eInfochips, the subject of FPGAs came up. Shroff said that in his business, he saw systems houses moving away from ASICs to FPGAs. "The costs of doing an ASIC have simply become too high for many designs," he explained. So in areas such as broadcast equipment, surveillance, and health care, Shroff has seen large FPGAs displacing medium-sized ASICs.

This has not been an easy transition, though. Shroff said that as the largest FPGAs—the only ones that can offer SoC-like logic and memory density—come into use, placement and routing are "becoming a nightmare." The old concepts of programmable logic, from cut-and-try design to pushbutton automated placement, are simply breaking down in the face of the growing complexity and the extremely high timing and power costs of even slightly inefficient routing. This despite the FPGA vendors’ assurance that they have now put so many routing resources on the die that interconnect is no longer a limiting resource.

Shroff said that, ironically, the thing that seems to help most with the placement and routing of these large FPGAs is to have a design team with cell-based back-end design experience. "Standard-cell placement experience becomes vital on some of these projects," he said.

Shroff’s observations have an interesting economic implication. If the back-end flow in FPGA designs is becoming as complex and difficult as the back-end design for a cell-based ASIC, then the major savings in NRE have to come from other areas. The savings could come from front-end design, where the FPGA vendors have lavished resources on raising the level of abstraction, employing pre-qualified IP, and containing the entire flow in a single user interface. They could come from the impressive IP libraries that the FPGA vendors have assembled and supported. Or they could come from the fact that FPGAs recover their manufacturing costs from their unit price, rather than from up-front mask and wafer charges.

In the latter cost structure there is a built-in advantage: FPGAs are standard-product wafers, run in big lots. But for the largest parts, this may not be as big an advantage as it sounds: there aren’t that many of these aircraft-carrier FPGAs built, and the yields aren’t that great that the unit cost should be much lower than the unit cost of a significantly smaller ASIC die. Generally the packaging costs will be much higher. The big difference may be the mask charges and overhead from small wafer lots experienced by ASICs.

All this suggests some truth to the argument that fabless ASIC consolidator eSilicon, for one, has been making. If you use new techniques like multi-project masks and wafers, consolidate projects to reduce small-run costs, and shift costs from NRE into unit prices, the difference in cost between a moderate-sized SoC and a huge FPGA may start to disappear at a much lower volume than it used to. If that’s true, the big front-end cost difference between the ASIC and the big FPGA might turn out to be in the better front-end design methodology that the FPGA vendors have assembled. That has virtually nothing to do with the fact that the methodology supports a configurable, rather than an ASIC, piece of hardware. It is something an ASIC vendor, with equal resources, could do at least as well.