Actel FPGAs take signal processing into space
Actel’s program to provide radiation-tolerant FPGAs for aircraft and space applications takes another major step today with the introduction of two extensions to existing product families. In the first, the company will announce adding hard DSP macros to its RTAX line of rad-tolerant antifuse FPGAs. In the second announcement, the company will disclose a program to extend its family of ProASIC3 Flash-based FPGAs to many space applications.
The seriously-hard antifuse parts, called RTAX-DSP, range up to 4 million gates and carry newly-designed multiply-accumulate blocks. Each block performs an 18×18-bit multiplication to a 41-bit accumulator, and can be fractured into a pair of 9×9 units. One input to the accumulator can come from its own output, from another nearby MAC block, or from the logic fabric, allowing ganging of the units. The larger of the two devices in the new sub-family combines 4 million gates of logic fabric with 120 MAC blocks.
Actel director of marketing Ken O’Neill said that demand for greater signal-processing power was coming from the growing trend to site image processing, signal filtering, and software-defined-radio functions in orbital platforms rather than back on the ground. "The only alternative designers have had for this level of computing power has been to commit to a rad-hard ASIC, with substantial NRE and turn-around-time impact, or to consider triple-chip redundancy using advanced SRAM-based FPGAs," O’Neill said. "The industry had been considering that triple-module redundancy within a single SRAM FPGA was sufficient, but recent reports have documented cases of full-chip failure in SRAM FPGAs from single-event upsets (SEUs.) So putting all three redundant circuits in one chip is not an option."
The whole question of detecting and mitigating SEUs in SRAM FPGA configuration memory is an active area of research right now (see, for instance, here.) O’Neill’s argument is that particularly with heavy-ion radiation, it is possible for an upset in the configuration memory of an SRAM-configured chip to so disrupt the configuration that all or most of the chip ceases to function correctly. This would negate mitigation through triple-module redundancy with all three modules on the same chip. Counters to this threat include continuous read-back and cleansing of the configuration memory, but preclude 100 percent availability of the circuitry.
The RTAX family eliminates this problem simply by not having configuration SRAM cells. It’s configuration elements are non-reprogrammable antifuses, which have proven extremely rad-hard. The chips still require SEU-resistant latches and SRAM blocks, of course, and upset-and-transient-protected logic and registers in the MAC blocks. But taken together, the new chips with the MAC units should be as radiation-tolerant and as high in reliability as the existing RTAX family members, O’Neill expects. The company expects to deliver the development software for the new parts in November, and prototype silicon in non-hermetic packages in mid 2009. Full 883b-qualified parts are scheduled for the end of 2009.
The second family in the Actel announcement is for reprogrammable Flash-based FPGAs, ranging from 600 K to 3 million ASIC gates. "These devices are not as hardened as the RTAX family," O’Neill explained, "but they are rated for a maximum total ionizing dose of 20 KRAD." The parts are designed to exhibit no single-event latchup or configuration-cell upset at under 82 MeV-cm2/mg LET. "You do have the possibility of SEU in registers and memory in these devices, but you can handle it with triple-module redundancy, which may be automatically generated by our software. Since there is no mechanism for SEU inducing chip failure, there is no need for triple-chip redundancy."
This level of tolerance makes the parts suitable for pico-satellites and research platforms that have relatively short missions, for low-earth-orbit satellites, and for equipment that will operate in a shielded environment on longer, more distant missions, such as equipment inside the Ares and Orion launch vehicles.
There are two main reasons why designers might want a reprogrammable FPGA in such applications, O’Neill said. First, most development work gets done with reprogrammable parts for economic (OK, and personal face-saving) reasons. Having qualified Flash-based devices means that the design can go directly from terrestrial prototype to flight vehicle without having to be ported to a different FPGA architecture—a big savings in schedule and risk. Second, in some cases, mission managers are looking at using in-flight reprogrammability to extend the useful life of a platform by modifying the function of the on-board electronics. This is often an attractive option for research satellites, O’Neill suggested.
Since there are no netlist or programming-file differences between the standard ProASIC3 parts and the hardened versions, designers can begin prototyping designs today. Ceramic-packaged, flight-qualified parts will be available early in 2009.
One issue designers will have to keep in mind is that not all ProASIC3 IP will automatically work on the rad-tolerant devices. "We are still evaluating the IP libraries," O’Neill explained. "The issue is that as the total ionizing dose the chip has received grows, the circuit performance goes down. So the IP has to be able to continue functioning with continual degradation of path delays over the life of the mission."
