Mentor adds power-integrity to HyperLynx board-level tools

Mentor Graphics announced today that the company has added a set of power-integrity tools—doing both DC and AC analyses on power grids—to their HyperLynx PC board tool set. The tools are the result, according to Mentor director of business development David Wiens, of a continuing evolution in power distribution driven by the IC world.

Wiens said that not that long ago, there would be only a few supply voltages distributed around a typical complex circuit board. Each would have its own layer, so that except for exclusion zones and vias there would be a whole sheet of metal for each voltage. But today, he said, it’s not that unusual to see up to 30 different power rails on a board, with some as low as 0.8 V, and often with the lowest-voltage rails driving the least noise-immune circuits. In this environment it’s not possible to dedicate a board layer to each supply voltage, so the power networks get fragmented and packed, multiple voltages per layer.

At the same time, with increasing attention to power management, loads have become far more dynamic. Modern microprocessors slip in and out of power-save modes rapidly and without warning, making radical changes in load on various supply pins as the go. This puts demands not only on regulators but on the distribution network, the decoupling capacitors, and, ultimately, the copper shapes that have to deliver the current.

It is this troubling environment that faces board designers today. But Wiens worries that not many designers are ready for it. "In many ways power-integrity analysis is at the point where signal-integrity was ten or twenty years ago," he offered. "It’s something a lot of designers are going to have to get up to speed on quickly." Nor, Wiens thinks, will the industry’s traditional approach to new problems be very effective here. "Layouts are very design-specific, and power integrity depends on the shape of the metal," he argued. "A given shape doesn’t recur often enough to simply learn a repertoire of shapes that work and reuse them. Nor is it easy to develop an intuitive grasp of power integrity. So neither reusing patterns nor relying on the intuitive guru in the back room works very well."

For these reasons Mentor thought it worthwhile to present a major tool addition for the problem. Just as signal integrity had to be addressed with a toolkit, so now does power integrity.

Mentor’s answer is an option for HyperLynx that offers two forms of analysis: DC and AC. The DC analysis module identifies the current sources and sinks and does a current-density analysis to identify where there is enough copper in the design, and where crowding can become an issue. It also does a voltage-drop analysis to determine whether each active device will receive adequate voltage under operating conditions. The tool is designed to start out with a coarse mesh, which it iteratively refines, so that the user gets an early look at major problem areas and then can stay the course for increasingly fine-grained examination of more detailed issues.

The AC analysis employs a wizard to help the user build power-pin waveforms for the devices on a grid. It then examines the layout for AC power integrity, allowing the user to optimize the placement and size of decoupling capacitors, as well as to contemplate layout changes to reduce supply noise coupling. It is possible to use co-simulation to inject noise from aggressor signal nets into the power grid as well to refine the analysis.

The arrival of comprehensive power-integrity tools raises another issue: design intent. In aggressively power-managed systems, not only may regions of the board be switched between power rails or powered-down during operation, but individual chips can entirely change their power-grid characteristics during operation, often very quickly. This puts a premium on the ability of the design team to communicate what they intend to happen in each power mode—and what the state transition table looks like—to the board designers. For either the DC or the AC analysis to be accurate, this information has to get reflected in the waveforms and levels the power-integrity tool uses. In many cases, this requirement will simply mean that the chip-level designers will get more and more involved in design and analysis of the circuit boards.

In addition to the power-integrity tool, by the way, Mentor also announced enhancements to the signal-integrity kit for HyperLynx, adding a set of wizards and a complete validation environment for DDR2/DDR3 signal integrity. The package should allow designers to simply describe the design and get a pass/fail report on a DDR interface, Wiens said.