USB 3.0 SuperSpeed IP puts a date on the next USB technology node
In was inevitable than anything as successful as USB 2.0 had to have a revised, higher-speed version. And so it does, on paper: SuperSpeed USB 3.0. This interface standard calls for operation of the USB protocol over standard traces at up to 5 Gbits/second, along with full backward-compatibility to USB 2.0. The applications are more or less obvious. Think of any situation in which consumers have to wait for a file to transfer between devices. HD video cameras, video-rental kiosks, and removable disk drives are examples. But the question that sticks in the SoC designer’s mind is "how the heck am I going to implement that?"
Synopsys would be delighted to help, today introducing a complete IP platform for the interface, including device controller, Phy, driver software, and even OSCI transaction-level models. The word "introducing" needs a bit of explanation here, however. The company is actually announcing that the IP will be available to early customers in the first half of next year, and to everybody else in the second half. Right now they are just tossing their hat in the ring.
Part of the reason for the early announcement, perhaps, is the way Synopsys sees SuperSpeed rolling out. Product marketing manager Eric Huang said that he suspects the first devices to use 3.0 will appear in the third quarter of next year, based on discrete interface chips. And Huang dropped a broad hint that an interface IC vendor who didn’t want to invest in coming up to speed on the new technology would certainly make a good early customer for the Synopsys IP. Widespread use of the interface, of course, will require integration into SoCs. And Huang expects the first SuperSpeed-capable SoCs to start design during 2009, showing up in products in 2010.
Aside from the obvious difficulty of the Phy, the interface presents some interesting challenges to the IP design team. One of these is simply variety. At 5 Gbits/s, USB 3.0 is no longer purely a PC peripherals interface, or even a media interface. It can play in the mass storage space as well. But this range of applications requires quite a range of device controllers: from very heavy-hitting with big buffers in the disk drive space to very low-power with essentially zero standby power in the mobile media-player space. So the device controller block has to be highly configurable.
That means not only options in scaling the buffer memory in the block, it means configurability in the functions and the power management as well. Synopsys has taken a fairly conservative approach to power management in the synthesizable device controller block, offering the option of dual-rail supply voltages, a power-gating mode that Huang said shuts off about 95 percent of the logic in the block, and clock throttling. Even though clock throttling implies that real-time performance-needs information is available to the block, the IP doesn’t appear to implement dynamic voltage-frequency scaling. The design does, however, support UPF.
That backward-compatibility bit is another sticking point. There is so little in common between USBs 2.0 and 3.0 that the Synopsys team found it best to build two separate MAC blocks and two separate Phy blocks—one each for 2.0 and 3.0 for each function–in order to implement the interface. Only when you get past the MAC proper and into the flow control and bus interface do the two standards actually share hardware.
And that raises another issue. If you just dropped two Phy hard macros on the periphery of the die, side by side, according to Synopsys product marketing manager for Phy IP Gervais Fong, the Phy blocks would take up so much beachfront that they could easily occlude an entire side of a small die. So the Phy team had to modify the layout of the two blocks to make them long and narrow—just about a worst-case for high-speed signal timing—to minimize the beachfront. Therein lies an interesting physical-design war story, one suspects. But in any case, the work succeeded, Fong says.
In terms of raw technology, the 3.0 Phy is not starting from a clean sheet of paper, and so it is not entirely green physical IP. Fong said the design relies on Synopsys’s widely-used PCI Express Phy. So the circuitry is pretty well wrung out by repeated tapeouts.
A final point worth mentioning is the matter of application assistance. Of course dropping an interface of this speed into a customer’s chip design and package choice is non-trivial, and Synopsys has expertise in helping with that. More interesting problems may come up in areas where design teams are less familiar with asking help from IP vendors. For example, given the speeds involved, getting an SoC with a 3.0 interface to come in under power limits could become a joint project between the IP designers and the customer’s power-management engineers. Another interesting issue for customers will be dealing with the potential data rate of the interface back into the SoC. A thumbnail calculation says that operating at full 5 Gbytes/s on streaming data—like HD video, for example—one of these interface blocks could consume most or all of the real bandwidth of a 125 MHz AHB bus architecture. That’s a scale of dataflow that not all SoC architects are used to dealing with, and Synopsys may find itself doing some consulting far earlier in the design than it is used to. It’s easy to say you can moderate the impact by putting in bigger buffers. But with long streams of video, those buffers might become so large as to impact the layout, error- and yield-management decisions, and power-management strategy for the whole SoC. That should be fun all around.
