Notes from ESC Sidense: OTP memory IP slipping between the stereotypes

If you ask system designers today about one-time-programmable memory, they tend to think either of large, mask-programmed chips used for code storage, or of tiny amounts—bits or bytes–of embedded OTP used to store ID numbers, encryption keys, or trimming data on chips. But there is at least one version of OTP that fits in between those two concepts, and for that reason may not get the recognition it deserves: relatively dense, low-power OTP memory IP intended to be embedded on SoCs for execute-in-place code storage, or storage of large parameter tables.

This is the world of Sidense. Their underlying technology relies on a split-gate transistor—fabricated in vanilla logic processes—to provide stable, write-once-read-forever memory arrays. The company claims to have a range of active designs, using a median of about 128 Kbits of memory per chip. They currently support logic processes from 180 nm to 65 nm CMOS at foundries including TSMC, UMC, SMIC, and at least one of the Common Platform folks.

Since the technology offers fast read times, typical embedded processor cores can execute code in place from the memory arrays, eliminating the need for an external ROM, a significantly less-dense internal program SRAM, and a download stage at power-up. Since the arrays can be configured either for test-head programming or for in-circuit programming, conceivably you could give an SoC the latest code version at wafer test, leaving some of the redundant rows unprogrammed, and then program in patch code remotely in the field, allowing a certain amount of code maintenance in the OTP on-chip memory without resort to external ROMs. Once you are really confident in the code, should that ever happen, you can switch to a mask-programmed version of the memory array.

The memory technology appears to be quite robust in process migration, according to Sidense president and CEO Xerxes Wania. The IP has already been ported and used in a number of technologies from, as mentioned, 180 nm to 65 nm. The company’s modeling efforts indicate that it will work at 45 and 40 nm as well. They should know for sure soon, as Wania says Sidense is about to tape out their first 40 nm tests.

If there is a downside to the story, other than committing an SoC to a single-source memory technology from an IP company, it is the programming time. Wania says that the rule of thumb is about 50-100 microseconds per bit, which can stretch out rather if you are programming an entire 12-inch wafer of good dice with half-megabit memory arrays on them. There are ways around this by dividing the memory into independent banks and using multi-site programming, of course.

Combining density, speed, inherently low power, and OTP functionality, the IP should be a boon for some SoC applications. But by managing to violate most of what people expect from OTP memory, Sidense has to work to be considered. It might be worth a look.