The road to 32 nm: good-bye to performance scaling, analog, and SoI?

As usual, Applied Materials put together a fascinating panel at the International Electron Devices Meeting last week. The topic in question was what roadblocks stood between us and the 32 nm node. The answers were sobering.

The panelists were Venu Menon from Texas Instruments, Been-Jon Woo of Intel, Dmitri Antoniadis of MIT, Zoran Krivokapic from AMD, IBM fellow Ghavam Shahidi, and Farhad Moghadam from host Applied. The panel was challengingly moderated by Scott Thompson of the University of Florida.

Faced with the problem of identifying the most likely roadblocks, each panelist had his or her own key concerns. Menon pointed out the learning curve on immersion lithography, the dangers of relying on ever more channel stress, and the fact that we still have not converged on a formula for the high-k/metal-gate stack. But he also singled out SRAM as a problem area, saying that cell stability could no longer be accomplished by process alone—it would require help from circuit designers.

That theme would be echoed by all the other panelists, in a variety of contexts. MIT’s Antoniadis looked at the question from a physics point of view, stating that electrostatic integrity at 32 nm required electron velocity that approached the ballistic velocity of the particles. He went on to warn that NFETs in particular would not meet performance requirements unless something drastic was done about contact resistance, and that ever more strain would be required. But, he observed, and Krivokapic seconded, that shrinking geometries left little room for the stress caps everyone has been planning to use to apply the stress. So new silicides and embedded layers would have to take up the slack.

IBM’s Shahidi described 32 nm as, at least initially, a shrink of the industry 45 nm process, saying there would be no multi-gate transistors, fancy substrates, biaxial stress or voltage scaling in the initial form of the process. He also said that there could well be no performance gain between 45 and 32 nm, and no low-power option. Moghadam summarized this conservative approach by saying that by 32 nm, electronics would not be about new devices or new lithography, but about new materials.

During the discussion several panelists repeated that we have about seen the end of voltage scaling. That limitation will have increasingly drastic implications as we continue to try to scale other parameters. In particular, Menon commented “As we tweak these devices for digital operation, we are making transistors that are not compatible with analog design. For instance, things we are doing are driving up 1/f noise.”

Asked if high-k dielectrics and metal gates were the answer, the panel was cautious, saying that the combination doesn’t buy much until 32 nm, but might become necessary then, even though there are still no clear solutions for PFETs. Similarly asked about multigate transistors, Krivokapic let loose on the whole idea. “When you design these devices, the parasitics just blow up,” he stated. “Techniques to increase the drive current just increase the capacitance, and overall the speed declines, a lot. How is it that we never see AC characteristics reported in papers on these things?”

In summary, the panelists saw the center of responsibility shifting from process engineering to circuit design. Menon suggested that process engineers might present circuit designers with a menu of five different kinds of transistors. More dire, he predicted that designers would be presented with entirely gridded layouts in an attempt to absorb some of the increasing variability coming out of the lithography steps. “We provide the density, but the performance is someone else’s job,” Shahidi summarized.

Perhaps the big news of the evening was that when asked if SoI would still be advantageous at 32 nm, AMD’s Krivokapic declined to comment. Shahidi from IBM, another present-day SoI champion, stepped in to say that SoI would still offer shallower junctions and fewer isolation wells, but admitted that it would continue to present barriers to the very circuit designers everyone was counting on to bail them out on performance.

Clearly there are still at least some poorly-marked turns on the road to 32.