A new generation for Design Compiler

Synopsys this morning announced a new release of the company’s cornerstone product: Design Compiler 2010. In response to the many new issues created by advanced geometries, this new release offers two significant changes: integration of a substantial chunk of IC Compiler technology into DC—in effect redistributed the workloads between DC and ICC—and an effort to adapt the entire DC package to multicore servers.

The primary problem DC 2010’s changes address, according to Synopsys vice president of engineering for RTL synthesis and test automation Eyal Odiz, is one of iterations. In creating the netlist and supporting files DC passes to ICC, the synthesis tool must estimate delay, crosstalk, and layout congestion in order to make sure the synthesized design is viable. Otherwise ICC will not be able to close the design, and you will have to go back to RTL, change code, constraints, or directives, and try again. The more accurately DC does its estimations, the fewer iterations.

This is one of those trade-offs. At one extreme, you can make a really fast synthesis tool that uses extremely simple models to estimate timing, and simply ignore other effects—exactly what we had a few years ago in the days of wirebond models. But with modern processes and designs, in which wire impedance dominates delay times and signal coupling is represented by switching windows, simple models will not correlate with the complex models used in the place/route tools. The synthesis tool will pass along a design that has no hope of working, the P/R tool will inform you of this, and repeat until done.

At the other extreme, you could design a synthesis engine that simply called ICC every time it needed to estimate the timing or area of a net. This would almost guarantee first-pass success, but in exchange for enormous run times and memory hoofprints. The art of creating a tool chain lies in finding an elegant balance between the two extremes that fits the issues the process technology has created.

That is of course what Synopsys is attempting to do with DC 2010. Odiz says the synthesis tool includes a partial placement engine. DC accepts floorplan data as a DEF file or as tcl, and then works through I/O placement, blockages, and high-fanout nets, down into the details until everything is placed. "This is not a fully legal placement as in the Physical Compiler days," Odiz explains. "It’s just a better starting point for ICC. From here ICC will legalize the placement and optimize timing and congestion." One advantage of having all this analysis in DC is that Synopsys provides a layout editor within DC so you can view congestion hot-spots, modify the floorplan, and see the results without leaving the tool.

Interestingly, Synopsys doesn’t seem to have any plans to take the idea all the way back to the level of Physical Synthesis, apparently for sociological reasons as much as technical ones. "We went back to separate synthesis and placement when we introduced Topographical Technology," explains senior director of marketing Gal Hasson. "The division reflects the different skill sets of designers. In most teams, the synthesis team has less knowledge of the physical aspects of the design than the back-end team has, and customers seem to prefer that the tools reflect that."

The placement seed that DC passes to ICC has already had timing, area, and coupling-capacitance analyses performed, in some cases using the same basic algorithms ICC will use. All this work creates about a 10 percent penalty in DC runtime, Odiz says, but it allows a 30 percent reduction in run time for P/R. More important, the correlation between DC 2010 and ICC is said to be excellent: Synopsys claims under 5 percent difference on both timing and area between the two tools, without being specific about the designs or computations used to come up with that number. That result would certainly suggest fewer iterations.

This deeper integration of ICC into DC is just beginning, Odiz says. "We will have to bring in more estimation in the future, for example starting to do multi-layer analyses."

Finally, Synopsys announced that all the pieces of DC 2010 have been threaded for parallel operation on up to four CPU cores. Wider parallel execution will be coming in the future, Odiz says. But today you can double your throughput on DC 2010 by moving from a single core to a four-core machine.

Even with this speed-up, DC is still not a full-chip tool. "We recommend using DC at the physical block level: the same blocks you would use in ICC," Odiz says. The potential gain here isn’t in making the blocks a lot bigger. It is that you may only have to pass each block through DC once—at least until the ECOs start.