PMC goes multicore with RAID controller
Gradually but inexorably, multicore SoC architectures are seeking out all the applications in which enough independent threads exist to entertain multiple cores. Not only is this happening at the extreme high end of the embedded computing spectrum where there simply is no other way to reach the desired performance level, but it’s also taking place in mid-range applications, where several small cores can be cheaper and more energy-efficient than one fire-breathing CPU. Consequently, embedded-application developers are wrestling their code into multiple threads, and SoC developers are providing cores to match the threads.
A case in point, as PMC-Sierra announced today, is RAID controllers. This might not seem like a compute-intensive application at all. You have a bunch of lumbering disk drives sitting there, and maybe 20 of them together can’t quite manage 10k I/O operations per second (IOPS.) The DMA controller may stay busy, but the control computations just aren’t that challenging.
But PMC-Sierra product marketing manager Cameron Brett points out that the plummeting price of NAND Flash is changing the picture. Consider a high-performance RAID disk array of, say, 20 rotating drives. If you are really after performance, you will use the drives in short-stroke mode-that is, employing only the very outermost tracks, where the data rate is highest and where you can minimize seek time. That gives you good performance, but you use less than 10 percent of each drive’s raw capacity. For about the same price, you could get four 100 GByte Solid-State Drives (SSDs,) connect them up in a RAID configuration, and get a bit more usable capacity: about 300 GB. But the SSDs would slash your power consumption from something over 200W to about 10W, and they would increase your available throughput from about 9k IOPS to about 90k. Suddenly the performance of the RAID controller is an issue.
PMC has responded with a new line of RAID controller ICs, a joint development with IBM to produce a multithreaded version of IBM’s RAID firmware stack, and a low-profile PCIe gen-2 8-lane card to plug into x86 servers. The products are aimed at RAID configurations of SSDs, as well as conventional HDD RAID arrays, using either SATA or SAS, including the 6 Gb SAS generation. That means the controller has to deliver performance. “Each SSD is capable of 15-30k IOPS,” said PMC director of product marketing Zaki Hassan. Even with a four-drive SSD array you have a significant transaction rate.
To support the RAID stack at this throughput, PMC has teamed three multithreaded MIPS 34k cores, clustered around a high-speed switch. Rather remarkably, the chip uses only local memory, without external DRAM, Brett said. The board that uses the chip, the BR5225-80, measures in at over 136k IOPS on 4k random reads, and over 44k IOPS on the 4k OLTP random 2:1 metric. Additionally the chip supports one end of a Web-accessible, SMI-S 1.4-compliant management utility that runs on the host server.
One of the advantages of the multicore approach is that until you run out of threads, it’s scalable. Accordingly, PMC is planning another SoC, this time with four MIPS cores, L2 caches, and a DDR2 controller. That one should hit 300k IOPS, Brett said.
