A venerable CPU core meets a new FPGA
One test of an FPGA product line has been porting a microprocessor IP core to the chip. CPU cores traditionally have been very challenging objects for programmable logic. They can rely on structures that not all FPGAs support gracefully. They can have critical timing paths in very dense clouds of logic. They are often big. Such issues years ago induced Altera and Xilinx to create proprietary small RISC cores for use in their chips, and led Actel to work with ARM to optimize a soft ARM-7 core for their array. More recently, the fashion has been to embed a more complex ARM core as hard IP outside the array rather than trying to make the CPU synthesizable.
Still, the attraction remains to picking up an industry-standard CPU in synthesizable form and dropping it into an FPGA flow to get a good, low-cost embedded processor. Such opportunities exist. One is Freescale’s wonderful little ColdFire core, a 68000-compatible 32-bit CPU that is heir to an enormous embedded-computing infrastructure. The core is available through IPextreme, which announced recently that it had ported ColdFire to Tabula’s ABAX FPGA.
This is an interesting exercise for a number of reasons. Porting a CPU, as mentioned, is always a good exercise to learn about a programmable architecture. And both ColdFire and ABAX are special cases. ColdFire is a very old design of elegant simplicity. ABAX is a radical new design which claims to encapsulate its internal complexity so the user sees only a conventional-looking FPGA.
It seemed a good idea to speak with Pierre-Xavier Thomas, vice-president of engineering at IPextreme, whose team actually did the port. Thomas explained that when IPextreme picks up a new core for their product line, his team generally runs the IP RTL through a number of widely-used flows-both ASIC and FPGA-to understand what their customers will see and to generate scripts capturing the core design intent for various flows. So Thomas’s team was familiar with the ColdFire core in a number of contexts already. “It is a small core, and the RTL is clean and well-partitioned. Everything is synchronous and the clocking scheme is simple,” Thomas says.
So how did the ColdFire port onto ABAX go? Without surprises, according to Thomas. Initially his team worked with a team from Tabula, “because the tools are new and they wanted to watch us,” Thomas explains. But the ColdFire IP came up quickly, using the standard Tabula flow. FMAX was around 80 MHz-to the delight of the Tabula engineers-without any hand optimization. The team let the Tabula tools map the design automatically, so they never had to be involved in ABAX’s fascinating time-domain-multiplexed internal structure.
That is a proof point: a simple but highly useful soft core, out-of-the-box tool flow, and a good result. Thomas says there is the potential to go faster with hand-crafting. But part of the point is that most users won’t need to.
