Device-level extraction becomes an issue for SoC designers

Parasitic extraction is not generally a subject to stir much interest among SoC designers. Front-end designers rarely think much about it. Back-end folks know extraction in terms of full-chip tools that create the parasitic-capacitance data for static timing analysis. But there is a different kind of extraction tool that hardly anyone thinks about: transistor-level extractors. These computationally-intensive tools are designed to give highly accurate resistance and capacitance estimates on the most detailed structures-transistors, capacitors, and the first few layers of interconnect. Today they are used primarily by cell designers, analog circuit designers, and a handful of custom-design specialists. But their importance, and to some degree their use, may be about to spread far beyond these niches. So it is important to a wide range of designers to keep an eye on what is happening at the transistor level.

A number of forces are simultaneously challenging the accuracy and capacity of the traditional tools in this space. This is important because errors in extraction at the cell level can become systematic errors in timing analysis, accumulating across a structure rather than averaging out. So choices that cell designers, designers of some analog devices, and custom data-path designers make in characterizing their designs can end up impacting timing closure at the chip level. And if those choices were made in an IP design, unknown to the chip design team, things can get genuinely complicated.

The new forces are-no surprise-mostly the offspring of shrinking geometries. At the transistor level, diffusions, contacts, and metal segments are getting so close together that they are forming complex capacitively-coupled networks. “We are seeing more cases of not just metal-to-metal coupling, but metal-to-device and device-to-device interactions,” says Dermott Lynch, vice president of sales and marketing at tool vendor Silicon Frontline. “If you analyze an image sensor pixel, even the color filter you put over the cell impacts the electrical behavior of the cell.”

Further, understanding what is going on within a structure is getting harder. Metal segments are so narrow that non-uniform current distribution within a piece of copper can be significant in the capacitances. And determining the actual shape of a structure at these geometries is a further challenge. The cell designer knows the ideal polygon geometry from the place and route files. But the actual chip won’t have nice right polygons-it will have a collection of cylinders, blobs, and misshapen ellipsoids that were the best the process engineers could do with their litho, etch, deposition, and polishing magic. The extraction tools can’t get accurate results unless they know the real, curved surfaces of the structures, not the ideal planar surfaces. So designers have to apply process-specific corrections provided by the foundry-in foundry-specific formats-just to get the real geometry so they can start to work. This is not data the foundries are happy to share, since it tells a great deal about their process controls. So the accuracy of the geometry the solver starts with may depend in part on the relationships between the foundry, the extraction tool vendor, and the design team.

The size of the problem is also becoming an issue. When the majority of coupling capacitances that influenced performance were actually in the transistor models, explains Mentor Graphics Design-to-Silicon vice president and general manager Joe Sawicki, it made sense to apply a detailed field-solving tool, such as Synopsys’s Raphael, to just the transistor. Then the cell designer could use a less exact extraction approach for the interconnect. But with metal-to-device interactions and the growing dominance of interconnect-Sawicki says that at 28nm about 70 percent of capacitance is in the interconnect, not in the devices-it is necessary to apply a detailed solver to entire cells, and sometimes to much larger structures such as custom pipelines, A/D converters, and memory arrays.

Therein lies a problem. Extraction tools have in the past been of two categories. There have been fast, large-capacity tools that work by pattern-matching: recognizing a pair of shapes near each other and consulting a table to estimate the capacitance between them. These tools are generally sufficiently accurate at metal-3 and above, where the long paths that dominate timing tend to average away errors. But this technique won’t give adequate accuracy at the device level. “Designers are asking for within 10 to 15 percent of silicon on individual coupling capacitors, and overall extraction within 2 percent,” Sawicki says. Some analog structures, such as high-resolution A/Ds, can be much more demanding than that, according to Lynch.

The second category of tools, such as Raphael, were designed to meet the more stringent requirements at the device level. These field solvers create a finite-element mesh through the structure-often in three dimensions-and then solve Maxwell’s Equations by successive approximation on the elements of the mesh. Such tools will get more accurate the longer you let them run, so they can be extremely good, if you are patient. But they are very slow in comparison to pattern-matching tools. Analysis of a single transistor can take hours.

That leaves an obvious problem: neither category of tools is appropriate to the challenge we face now. Not surprisingly, entrepreneurs have responded, looking for alternative ways to solve Maxwell’s Equations with less computation but the same accuracy as reference field solvers.

The obvious approach, time-honored in other types of finite-element analysis, is simply to find ways to do less work. You don’t need as fine a mesh in areas with a small electric field gradient, for example. By recognizing symmetric, rotated, or nearly-duplicate features you can reuse large blocks of computations. There are other, much cleverer techniques as well. This appears to the sort of approach Peter Shi took with his start-up, Pextra.

Early this year Mentor quietly acquired Pextra, and this week the big company announced their version of Pextra’s extraction tool as Calibre xACT 3D. Mentor says xACT 3D runs nearly four orders of magnitude faster than the reference solvers, can analyze not just whole cells but whole IP blocks-even blocks the size of an ARM core-and that the code is written to exploit multicore servers. Sawicki stated that xACT 3D’s deterministic algorithm runtime scales linearly with the number of transistors in the model and the desired accuracy, and almost inversely with the number of CPUs.

There is another well-known approach to fast field solving called a random-walk algorithm. This is used, for example, in Magma’s QuickCap. This algorithm pseudorandomly explores the electric field in the model, so it has the peculiar characteristic that the longer you let the algorithm run, the higher the certainty of the results at a given accuracy. Silicon Frontline last October announced a full-chip, sign-off-quality extraction tool based on a refinement of the random walk approach. The company makes performance and accuracy claims similar to Mentor’s claims for xACT 3D. Both tools are included in different portions of TSMC’s just-announced reference flows.

The next challenge for extraction is already on the horizon. While cell and IP designers and even some chip designers are switching to the fast 3D solvers for extraction, routers continue to use pattern-matching estimations for R and C internally. Different algorithms means different results, which means iterations through routing and sign-off analysis, or worse. But the fast solver algorithms today are probably not fast enough to call from inside the router at acceptable accuracy. Hardware acceleration may be necessary.

In another direction, device designers are beginning to use finite-element modeling to estimate the mechanical stress on the channels of transistors. Stress, which influences carrier mobility and hence transistor performance, is getting extremely layout-dependent, and so is hard to estimate from table look-ups. With fast 3D solvers it may be possible in a single analysis to mesh a cell, solve for its channel stresses and electric field densities in one pass, and thus develop a complete, layout-accurate model of the cell. With the sorts of multi-finned 3D transistors envisioned for 20nm, such analyses may be necessary.

Whatever the future, it is already clear that the cell designer’s and IP developer’s choice of extraction tools-not just which algorithm but where to use which algorithm-can have an influence on the quality of the timing models that these groups pass on to SoC designers. And so those decisions on the part of remote design teams can influence timing closure and accuracy to silicon for the whole chip. We just added to the list of questions you have to ask your IP providers.