Samsung leads the pack with 32nm HKMG announcement

The scramble to the 32/28nm node gained an official leader this evening when Common Platform member Samsung announced that it has completed qualification of its 32nm high-k/metal-gate (HKMG) process. “The process is now qualified in the manufacturing fab-the 300mm S-Line in Giheung [Korea],” declared Samsung vice president of foundry services Ana Hunter. The announcement beats by a nose two entrants who chose to announce HKMG at 28nm instead of 32. TSMC is still expected to enter risk production by the end of June on their 28HP process, their first HKMG but second 28nm offering. And Common Platform teammate Globalfoundries plans to start risk production sometime in the second half of 2010 on their 28nm HKMG line. UMC reportedly intends to enter risk production by the end of 2010 as well.

Samsung chose not to follow TSMC’s decision to bypass 32nm and go directly to the 28nm half-node. Instead, while rivals are scrambling to start risk production at 28, the Korean giant will be building production time on HKMG at the slightly larger geometry. “We believe the learning at 32nm is worth it,” Hunter said. “This process uses the same gate module and back-end-of-line as 28nm, and the design rules migrate directly from 32nm to 28nm.” Consequently is should be easy for both Samsung and customers to migrate the half-step from 32 to 28 when they wish to. The company has said previously that it expects 28nm production start in the first half of 2011, with Xilinx FPGAs as the first commercial product.

Beside the 32nm vs. 28nm issue, another major debating point divides Samsung and the Common Platform camp from TSMC: the order in which the process constructs the transistor. Samsung is in the gate-first clan, while TSMC has developed a gate-last process. There have been reams of papers on the relative merits of the two approaches, but both foundries claim advantages for their own ways. Quite probably gate fabrication will remain a second-order issue, far less important in purchasing decisions than the traditional schedule, price, IP availability, power, and performance.

Samsung’s qualification pipe-cleaner, Hunter said, was the same IP-laden SoC design the foundry employed on its 45nm process. The design includes an ARM 11-76 CPU, Synopsys USB 2.0 OTG IP, and many Samsung-developed blocks, including DDR PHYs. Digital portions were synthesized using ARM logic libraries, and the chip employed ARM memory compilers and I/O libraries.

Hunter said Samsung used available commercial tools to take the original SoC netlist to its 32nm tapeout, including Galaxy placement and litho-aware routing and Calibre DFM rule-checking. In the more detailed library cell development Samsung and ARM used both Calibre DFM for checking, and statistical static timing analysis for timing. The Samsung team also used statistical timing analysis for full-chip timing closure. “We’ve used statistical timing internally since 65nm,” Hunter explained.

The results on the trial SoC reflect the predicted behavior of HKMG processes. Hunter said the 32nm chip consumed 30 percent less dynamic power and 55 percent less leakage power than its 45nm predecessor at the same operating frequency. But she added that this was not entirely a simple comparison. Both 45nm and 32nm chips started with the same netlist. She explained, “The 32nm design implemented multi-channel-length power reduction, employed multi-threshold libraries, and used adaptive back-bias techniques,” in pursuit of those power reductions. These techniques could have contributed a significant portion of the overall power savings, and are applicable at the older node.

The announcement answers the question of who will qualify first, at least subject to arguments over whether 32nm really counts compared to 28nm. But it does not yet resolve the longer-term questions about for whom the new node even matters. Clearly a few designs, such as leading-edge FPGAs, graphics processors, and CPUs have to go there for marketing reasons. For those same reasons, those designs will almost certainly go directly to 28nm, even if there is no significant increase in density or decrease in power. Performance will almost certainly be a wash by the time you get down to apples-to-apples. That leaves the same old questions: schedule, price, IP availability, and power. Power may also be nearly a wash, if you apply the same degree of low-power design expertise to the design at either 32nm or 28nm. So the question may simply devolve to a race down the learning curve and to gather up physical IP-a race in which size and reputation certainly count most, but in which a material head start might impact the customer’s cost and schedule more than any difference in process technology.