Synopsys tunes back-end tools for DAC

Synopsys starts this year’s Design Automation Conference with a series of product announcements that individually represent incremental advances on some existing back-end tools, but taken together-especially in light of recent releases from other vendors-suggest an important shift in direction for the practice of SoC design. In all, the company announced enhancements to four products: PrimeTime, Liberty NCX, Nanotime, and Raphael.

Probably the largest set of changes goes into PrimeTime 2010. First on the list is a very significant performance and capacity boost. Much of this speed-up, according to director of marketing Robert Hoegenstryd, comes from the way the tool handles the assembly of blocks into the full chip. Traditionally to close chip timing, the back-end team runs static timing analysis on the flattened full-chip design files. But doing it this way ignores the fact that the team by this point has already done detailed timing on the individual blocks they are putting together. PrimeTime 2010 tracks these individual block closure runs, and promotes the block-level timing and constraints to the full-chip level. Just by this act of reuse, Hoegenstryd said, the new PrimeTime can increase performance by a factor of five to ten. Further, this link between block and chip-level allows PrimeTime to automatically update the context for an individual block as the chip is assembled, and the process makes it easier for back-end designers to understand the block-level constraints in context and to recognize conflicts, added vice president of engineering Ken Rousseau.

Other changes to PrimeTime focus on improving performance for overall closure. Improvements to Advanced on-Chip Variations (AOCV), PrimeTime’s non-statistical approach to margining for on-chip variations, have made the margining process more aware of the impact of the broader context as the chip is assembled. “AOCV now has an intelligent way of adjusting margins when you assemble the blocks,” Rousseau said. And finally, Fix-ECO is a new light-weight feature that allows you to work across timing scenarios to make fixes to timing problems inside PrimeTime 2010, without having to drop back into the Place-and-Route tool.

Other significant speed-ups have been made in other areas. Hoegenstryd said a new release of the Liberty NCX system is seven time faster, and delivers models four times smaller, than the previous version. Transistor-level STA tool NanoTime is improved. And Synopsys has announced a new 3D field solver for detailed extraction, Rapid 3D. Hoegenstryd said this rewrite of the gold-standard Raphael has 20 times the single-CPU performance of its predecessor and is parallelized to scale well with added CPU cores.

While the emphasis in front-end tools this year has been on driving increased adoption of ESL flows, the back end of the tool chain seems intent on easing the job of integrating large IP blocks into a finished chip. One tries to change the way designers work, the other tries to make the work they must do come out better.