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Heard at DAC: another try at embedded FPGA IP for SoCs

June 17, 2010

The concept of integrating an FPGA into a platform SoC has immediate appeal. Most of the functions in an SoC-CPUs, memories, standard accelerators, even many interfaces-stay exactly the same across a wide range of customer requirements in a given application area. Only a few hardware requirements, such as an accelerator for a proprietary algorithm, perhaps, or a clever DMA engine or unique I/O controller, must change from customer to customer. It would be great to have a moderate-sized FPGA on the die that could implement such variations without mask spins, and without the chip crossings and added package count of an external FPGA.

In fact this idea was quite fashionable several years ago. But it went hard aground on a number of difficult shoals. FPGA fabric design is difficult. Even after you decide on a logic cell and interconnect architecture, the electrical design is challenging. A good blend of density, power, and speed is elusive. And the passgates used in the interconnect want special process tweaks, or interconnect speed becomes an issue. These considerations led most attempts at embedded FPGA fabric to be custom designs delivered as hard IP. But hard IP has to be redesigned for every process variant. And since the block you have is never exactly the block any customer wants, you end up redesigning for every design win as well.

But recent work by a French start-up, Menta, may have finally overcome many of these problems. Begun in 2005 with technology from local university research, Menta has produced a tool very like a memory compiler: a parameterizable FPGA fabric generator that can construct a block of FPGA fabric by assembling tiles, complete with block RAMs and embedded cell-based functions, and using only a normal logic cell library. The tool includes both the compiler to create the FPGA block and the programming flow to turn logic netlists into configuration bitmaps for the FPGA. No special process tweaks, customer cells, or hard IP blocks are necessary. Along with generating the netlist to create the FPGA fabric, the tool also creates place-and-route directives and constraint files to ensure that the fabric emerges at tape-out in good condition.

Menta has clearly focused on flexibility. The generator lets you select the size of your FPGA fabric and RAM blocks, and lets you design your own embedded function blocks-DSP units, crypto engines, or whatever. At a deeper level, the tool lets the more experienced FPGA user explore alternatives within the fabric. You can employ LUT-4 or LUT-6 logic cell structures, for example, or try different bus widths in the interconnect.

If you wish, you can further enhance the FPGA by allowing the generator to include some custom cells, such as area-efficient multiplexers, special pass transistors, and optimized SRAM bit cells. These cells are process-specific, of course, but they can significantly improve area, power, and performance of the fabric. The choice of technology for the configuration memory bits is also up to you. The generator can use conventional SRAM, Flash cells, antifuse cells, or MRAM-what ever your process offers.

The signal contacts on the block are registered, so you can treat the array as a black box for timing purposes. Menta says the fabric density is from 90 to 150 LUT-6 logic cells/mm2 in 130nm, and projects between 450 and 800 LUT-6 cells/ mm2 at 40nm. In practice, according to Menta manager of marketing and sales Christophe Bianchi, the ability to tune the logic fabric to the application lets you do much better than these numbers would suggest. “In applications, the area overhead for using eFPGA instead of standard cells is typically from seven to 20 x,” he said.

Menta claims several active customers, and has taped out test silicon at both 130 and 65nm, including at least one example using MRAM for the configuration bits in the FPGA fabric. The company is currently seeking a first-round investment to fund a 40nm tapeout. The design kit, including eFPGA Creator tool, tile library, and some sample cores is currently available from the company.

Posted by Ron Wilson on June 17, 2010 | Comments (1)
Industries: IC Design

June 24, 2010
In response to: Heard at DAC: another try at embedded FPGA IP for SoCs
RZ commented:

Brings back memories of Adaptive Silicon from ten years ago. At 130 nm, we found that 25k real gates worth of FPGA took up half a typical die. So the production target was looking more like 90nm for the companies we were talking to. Then the financial meltdown in 2001 took away that option. I wish Menta well.

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