EDA industry predictions for 2012

Each year, there are plenty of predictions being floated around by the industry pundits and for this year I will follow the Chinese proverb that says: a wise man once said nothing. Instead I am going to present to you some predictions made by a number of people in the industry. This resulted from a call for contributions I made through the EDA Designline a few weeks back and I will be presenting those in full over the next week. What I wanted to provide here is a summary of some of the trends that those contributors provided.

The first trend, and one that has been going on for some time, is a continued migration of functionality from hardware to software. Dr Markus Willems of Synopsys attributed this to “the needs to support multiple standards simultaneously (wireless, multimedia), use the same hardware platform for product derivatives (automotive), quickly adjust to evolving standards (wireless), and react to changing market demands (all applications).” Coupled to that is a change in the way that IP is being packaged and used. No longer are small IP blocks going to cut it. IP needs to be shipped with the software layers necessary to utilize it, and at the same time the IP blocks are growing from individual blocks to subsystems. This trend was highlighted by both Bill Neifert of Carbon Designs and Ed Bard of Synopsys.

Another trend identified by Lauro Rizzatti of EVE is that the network infrastructure will need an overhaul in 2012 due to the increasing amounts of high-definition video and other traffic. He also says that the increased rate of adoption of new technologies such as tablets, ultra-books, and their inherent demand for low-power solutions will help the EDA industry improve their importance.

Linh Hong of Kilopass sees advances in mobile payment systems, which scares the bejeebers out of me. He points out that KPMG says that mobile payments will be the most popular consumer application in 2012. If they are right, then I know I am getting old!

In terms of implementation, IBS states that 28-nm design starts will increase by 50% in 2012 and more people will be dabbling with 20 nm. The increased design sizes and complexity will create all kinds of pressure in the verification and test fields, requiring according to some - bigger and faster emulators, better flows for FPGA prototyping from others and a third group saying we need a whole new set of tools that are actually crafted to tackle the specific problems associated with large scale system assembly.

ESL continues to be an important thrust for the EDA industry and we can see lots of confidence coming from the companies that have tools in this area. Increased adoption of, and solidification of flows around, the TLM 2.0 standard is a popular theme. Different people point out different reasons for it and the new tools that it will push to the forefront. Closely coupled to this is the entire power issue. As Paul van Besouw of Oasys explains one aspect of the problem as “the big challenge in designing an SoC is whether the entire chip can be lit up at once (answer: no) and what to do about it.” While there has been a lot of focus on power optimization, he correctly says that power is a chip-level problem. Adnan Hamid of Breker Verification points out that “there are already automation tools available to design, implement, and analyze complex on-chip power management systems, but a complete lack of automated tools for verifying these systems in the context of the SoC functionality.”

Share your own thoughts on 2012 and comments on these predictions below.