Speed kills when it comes to printed circuit boards or chips

Speed kills, and when we are talking about printed circuit boards or chips, this is caused by distance. Last month, I was at DesignCon. This is the place to be for people who deal with high speed problems day in and day out. High-speed interconnect, design techniques and other tips and tricks that have been developed to insure that the integrity of the signals is maintained as it passes across the board, or from board to chip or across a chip.

The heart of the problem is that the world we try and create is digital. A 40GHz digital signal is not really running at 40GHz — it is dependent on frequencies much higher than that. That is because to fabricate a digital signal, with nice crisp edges and a fast rise time, requires harmonics of the main carrier frequency. These execute much faster than the clock rate that you think you are using. Without these harmonics you would have a sine wave operating at the desired rate, and that sine wave takes a long time to reach the desired state and loses its value almost as soon as it got there.

This is why these high-speed interconnect folks are always looking at eye diagrams. These show you what your digital signals really look like after they have traversed across an interconnect or been affected by their less friendly neighbors. Those higher frequencies tend to get attenuated, along with noise and jitter problems, as well.

To make matters worse, the tracks on the printed circuit board are not just pieces of copper. They are antennae, and have capacitance and inductance, both of which do not really like square waves. Add to that the fact that some of those signals happen to get reflected back down the interconnect, and some get radiated off the track as EMI — to interfere with other traces or the outside world. I could spend all day just talking about the bad effects brought on by signals that want to travel too fast, but unfortunately technology advancements require it, so we better get used to living with it.

I can remember dealing with such an issue when I had only been out of school for a few years. Back then clock speeds were a lot lower than they are today, but some of the problems were already beginning to rear their ugly head. The problem was with a clock line for a new processor chip that had just come back from the fab. When I looked at things on a logic analyzer, everything looked fine, but the processor kept locking in the wrong state on its interrupt lines. I only saw things in the digital world. I scratched my head for a while until a veteran board guy (who then ran the production facility) happened to look across my shoulder. He very quickly identified that there was a reflection problem along one of the traces that was causing the processor to latch in the data at the wrong time, and with a small capacitor inserted to damp those reflections, the problems went away.

While board design may seem very old school to many chip designers, the reality is that what happened to the board in the past is going to happen to chips in the future. Chips take longer to see many of the effects because the track lengths are a lot shorter, and thus the parasitics are less damaging to the waveforms. But if you ignore them, chips may operate slower than intended, work unreliably or experience low yields. As we see more analog blocks going on chip, the digital circuitry will be adversely affecting the more sensitive analog components and the recent power switching and optimization techniques are creating some new challenges. While many of these problems are found and fixed in the backend, it is probably time that all logic designers started to become more aware of what a digital signal really is and what happens to those signals in the face of realities.

Rambus recently released a book about this topic that you may find useful “High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting“, and I hope to be able to do a preview of this book in the near future.