Practical Chip Design
Brian Bailey explores how IC design teams work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?
Modeling in layers results in increased productivity
Productivity is related to the way in which we can model something and reliably go from that model to an implementation that meets all of the design goals. In the digital world, we have managed to incrementally increase productivity over time by raising the abstraction, improving the quality of the tools and removing tasks that previously had to be performed manually. Examples of the former are th ...... Read More
Comments (2)Top-down analog flows. Myth or reality?
There are very few designs these days that are not mixed-signal, meaning that analog functionality has been integrated onto the same die as digital logic. This is being done for several reasons, such as reduced cost, but perhaps more importantly, many analog functions now require some digital logic to allow calibration of the analog circuitry. Traditionally, analog design has been done in a bottom ...... Read More
Comments (3)June Conferences: DAC and Symposium on VLSI Technology and Circuits
Before we know it, it will be summer and that means conferences. First there is the Design Automation Conference (DAC) in San Francisco from June 3 until June 7 and then if you need to be warmed up after the cold San Francisco fog, you can head out to Honolulu for the Symposia on VLSI Technology and Circuits, which runs from June 12 through the 15. What you do in between is totally up to you. Desi ...... Read More
Comments (0)Power integrity -- How much does it matter?
If you have been following my month of power over on the EE Times EDA Designline, you will know that I have been featuring books that tackle the subject of power integrity. It should tell you something that I am featuring four of them — all very different books. This is perhaps a significant indication of the importance and complexity of this subject. Madhavan Swaminantha and A Ege Engin po ...... Read More
Comments (5)Time to rethink EDA flows and tool infrastructure
Recently, I have had the pleasure of talking to a number of entrepreneurs within the EDA space and got to hear some of their concerns and recommendations for people thinking about starting a new company. The results of those will be appearing here within EDN and in my EDA Designline blogs. One of the themes running through those interviews has been how much harder it is today compared to 10 or 20 ...... Read More
Comments (3)Functional verification concepts have to change
Last week was DVCon, probably the best conference of the year for those interested in functional verification. DVCon stands for Design and Verification Conference and it used to be that it concentrated on design. That was when languages such as Verilog and VHDL were the hot issues of the day. Today, languages such as SystemVerilog and SystemC are hot and verification methodologies such as VMM, eRM ...... Read More
Comments (2)Analog Bits appear everywhere in the chip
Last week I had the pleasure of talking to Mahesh Tirupattur, executive VP at Analog Bits. I have to admit that I had never heard of Analog Bits before, but the talk was quite enlightening. Many of the successful companies in our industry fly under the radar, and that has been the case with Analog Bits. They were founded in 1995. No VCs and thus no huge pressure to grow fast or quickly. They spend ...... Read More
Comments (6)Speed kills when it comes to printed circuit boards or chips
Speed kills, and when we are talking about printed circuit boards or chips, this is caused by distance. Last month, I was at DesignCon. This is the place to be for people who deal with high speed problems day in and day out. High-speed interconnect, design techniques and other tips and tricks that have been developed to insure that the integrity of the signals is maintained as it passes across the ...... Read More
Comments (8)Webinar: Power Issues for Chip and Board
Last week, I had the pleasure to record the first part of a webinar that will go live on January 31. This webinar talks about power and power integrity and the two speakers, Arvind Shanmugavel, the director of applications engineering for Apache Design (a subsidiary of Ansys), and Randy White, the technical marketing manager for measurement solutions focused on embedded systems at Tektronix, had s ...... Read More
Comments (4)An interesting trend with EDA books
Several EDA companies have been busy writing books recently and self-publishing them. Synopsys was the first to start this trend and many of their books have been co-written with their partners. A recent example was the “FPGA-Based Prototyping Methodology Manual,” written by Doug Amos and Rene Richter of Synopsys, and Austin Lesea of Xilinx. In a similar manner the “Verificati ...... Read More
Comments (6)EDA industry predictions for 2012
Each year, there are plenty of predictions being floated around by the industry pundits and for this year I will follow the Chinese proverb that says: a wise man once said nothing. Instead I am going to present to you some predictions made by a number of people in the industry. This resulted from a call for contributions I made through the EDA Designline a few weeks back and I will be presenting t ...... Read More
Comments (2)Random problems associated with small geometries
There were many alarms being rung, when features sizes were around 90 nm, about how smaller geometries were going to create a new set of issues. Today we hear increasing announcements about 20-nm designs being successful but I wonder if there is trouble around the corner, or if clever design can avoid the problems. I am talking about random particles in either the production process or in actual u ...... Read More
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