Practical Chip Design
Brian Bailey explores how IC design teams work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?
Webinar: Power Issues for Chip and Board
Last week, I had the pleasure to record the first part of a webinar that will go live on January 31. This webinar talks about power and power integrity and the two speakers, Arvind Shanmugavel, the director of applications engineering for Apache Design (a subsidiary of Ansys), and Randy White, the technical marketing manager for measurement solutions focused on embedded systems at Tektronix, had s ...... Read More
Comments (2)An interesting trend with EDA books
Several EDA companies have been busy writing books recently and self-publishing them. Synopsys was the first to start this trend and many of their books have been co-written with their partners. A recent example was the “FPGA-Based Prototyping Methodology Manual,” written by Doug Amos and Rene Richter of Synopsys, and Austin Lesea of Xilinx. In a similar manner the “Verificati ...... Read More
Comments (6)EDA industry predictions for 2012
Each year, there are plenty of predictions being floated around by the industry pundits and for this year I will follow the Chinese proverb that says: a wise man once said nothing. Instead I am going to present to you some predictions made by a number of people in the industry. This resulted from a call for contributions I made through the EDA Designline a few weeks back and I will be presenting t ...... Read More
Comments (2)Random problems associated with small geometries
There were many alarms being rung, when features sizes were around 90 nm, about how smaller geometries were going to create a new set of issues. Today we hear increasing announcements about 20-nm designs being successful but I wonder if there is trouble around the corner, or if clever design can avoid the problems. I am talking about random particles in either the production process or in actual u ...... Read More
Comments (1)ESL: The value of abstraction
I know I am as bad as other proponents for ESL, saying that abstraction is the key to almost everything and provides additional productivity, the ability to handle greater complexity, simulations run orders of magnitude faster, in fact the list of advantages is almost endless. But how often do we stop and question why this is the case and what could go wrong? Let’s start in the land of digi ...... Read More
Comments (5)The problem with the definition of ESL
How long have we heard the promises associated with a move to the Electronic System Level (ESL)? For the longest time it seemed as if all of the predictions about its growth kept moving out another year - every year. It always appeared to be just on the cusp of exploding, but never quite happened. And then all of a sudden, without any kind of fanfare it was here. People are talking about how they ...... Read More
Comments (2)Ubiquitous interfaces
It doesn’t matter where you look, interfaces are an important part of what we do. At the chip level, there are interfaces between the blocks, interfaces between the chip and the outside world, interfaces between digital and analog, interfaces between the electronics and humans. When we look at EDA tools, we again see a plethora of interfaces but they take on several new dimensions. We have ...... Read More
Comments (0)Does the EDA industry get any respect?
How many times have we heard that the EDA industry gets no respect? It is true that the EDA industry is tiny compared to the market that it serves. Several companies, CEOs and financial jugglers have tried to find ways to leverage a little more of the pie for the industry and for themselves. I wondered if this is a unique situation, or if we are actually quite normal. I started to think about the ...... Read More
Comments (4)Doing too much at once?
EDN welcomes Brian Bailey, an independent consultant working in the fields of electronic system level (ESL) methodologies and functional verification, to the Practical Chip Design blog. Brian has published six books, has four patents to his name, chairs standards committees, has produced educational courses, and has given talks around the world. He graduated from Brunel University in England with ...... Read More
Comments (2)In the dark over networks
Once again a large piece of North America-this time the US southwest and part of northern Mexico-has suffered a power outage due to network instability. According to the Associated Press, an operator near Yuma, Arizona took a capacitor off-line, following correct procedures. We may infer from the absence of reports of vaporized technicians, flying fragments of switches, or columns of flame that th ...... Read More
Comments (7)What is Fulcrum's real leverage?
At Hot chips last month Fulcrum Microsystems, purveyor of high-speed packet-switching ICs, made probably its last appearance as an independent company, delivering one last paper before the silicon gates of Intel clanged shut behind them. The paper described Alta, a 1 Gpacket/s packet-processing switch. And, in describing Alta’s development process, the paper also raised a fascinating questi ...... Read More
Comments (1)Exploring the Xilinx Zynq: software platform, or complex FPGA?
One of the enduring challenges of FPGAs with embedded CPUs has been the connection between the processor and the programmable fabric. A conversation at Hot Chips earlier this month with Xilinx vice president Vidya Rajagopalan suggested that Xilinx’s forthcoming entry in this rather exclusive derby, the Zynq 7000, is to be no exception. There have been two dominant approaches to the intercon ...... Read More
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