Practical Chip Design
Brian Bailey explores how IC design teams work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?
ESL: The value of abstraction
I know I am as bad as other proponents for ESL, saying that abstraction is the key to almost everything and provides additional productivity, the ability to handle greater complexity, simulations run orders of magnitude faster, in fact the list of advantages is almost endless. But how often do we stop and question why this is the case and what could go wrong? Let’s start in the land of digi ...... Read More
Comments (5)The problem with the definition of ESL
How long have we heard the promises associated with a move to the Electronic System Level (ESL)? For the longest time it seemed as if all of the predictions about its growth kept moving out another year - every year. It always appeared to be just on the cusp of exploding, but never quite happened. And then all of a sudden, without any kind of fanfare it was here. People are talking about how they ...... Read More
Comments (2)Ubiquitous interfaces
It doesn’t matter where you look, interfaces are an important part of what we do. At the chip level, there are interfaces between the blocks, interfaces between the chip and the outside world, interfaces between digital and analog, interfaces between the electronics and humans. When we look at EDA tools, we again see a plethora of interfaces but they take on several new dimensions. We have ...... Read More
Comments (0)Does the EDA industry get any respect?
How many times have we heard that the EDA industry gets no respect? It is true that the EDA industry is tiny compared to the market that it serves. Several companies, CEOs and financial jugglers have tried to find ways to leverage a little more of the pie for the industry and for themselves. I wondered if this is a unique situation, or if we are actually quite normal. I started to think about the ...... Read More
Comments (4)Doing too much at once?
EDN welcomes Brian Bailey, an independent consultant working in the fields of electronic system level (ESL) methodologies and functional verification, to the Practical Chip Design blog. Brian has published six books, has four patents to his name, chairs standards committees, has produced educational courses, and has given talks around the world. He graduated from Brunel University in England with ...... Read More
Comments (2)In the dark over networks
Once again a large piece of North America-this time the US southwest and part of northern Mexico-has suffered a power outage due to network instability. According to the Associated Press, an operator near Yuma, Arizona took a capacitor off-line, following correct procedures. We may infer from the absence of reports of vaporized technicians, flying fragments of switches, or columns of flame that th ...... Read More
Comments (7)What is Fulcrum's real leverage?
At Hot chips last month Fulcrum Microsystems, purveyor of high-speed packet-switching ICs, made probably its last appearance as an independent company, delivering one last paper before the silicon gates of Intel clanged shut behind them. The paper described Alta, a 1 Gpacket/s packet-processing switch. And, in describing Alta’s development process, the paper also raised a fascinating questi ...... Read More
Comments (3)Exploring the Xilinx Zynq: software platform, or complex FPGA?
One of the enduring challenges of FPGAs with embedded CPUs has been the connection between the processor and the programmable fabric. A conversation at Hot Chips earlier this month with Xilinx vice president Vidya Rajagopalan suggested that Xilinx’s forthcoming entry in this rather exclusive derby, the Zynq 7000, is to be no exception. There have been two dominant approaches to the intercon ...... Read More
Comments (3)Mentor, Calypto, Catapult C: is this an omen?
As more information emerges on Claypto’s acquisition of Catapult C from Mentor Graphics, the picture is growing increasingly complex. To begin with, this is not exactly an arm’s-length transaction. Mentor has been, and remains, a major investor in Calypto. So Mentor is not simply dumping the C-to-RTL synthesis technology in which it has invested so much; it will continue to have infl ...... Read More
Comments (0)The serverless data center: reflections from Hot Chips
The old paradigm was simple: if you had a big job you chose a big CPU. But that notion has fractured along many different lines. Last week at Hot Chips, we saw that even when building the most compute-intensive systems, architects’ fancies are wandering away from the behemoth eight-issue, out-of-order, speculating while psychically branch-predicting, 29-stage CPUs. The new darlings are smal ...... Read More
Comments (4)Does Agile Development make sense for SoC design?
One of the great debates of the last ten years in the software world has been the question of Agile Development. Given the growing role of software in an SoC project, it seems fair to ask if Agile techniques could-or should-be applied to the enormous OS porting, driver development, middleware integration, and application development projects that now envelop most SoC designs. For that matter, shou ...... Read More
Comments (7)Apache is part of Ansys: now what?
The August 1 completion of the acquisition of Apache Design Solutions by physical-modeling vendor Ansys brought a sudden end to a quick and surprising sequence of events. It also raised some fascination questions, not the least for Apache’s existing customers. A brief recap might help. In mid-March, Apache registered its intent to make an Initial Public Offering. The idea of a successful sm ...... Read More
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