All good designs must fail in your lab

In a previous blog post, I brought up the concept of receiver signal integrity. Since it seemed like a popular topic, I thought it would be worthwhile to dig a little deeper.In the world of transmitter signal integrity, we add guard-band to the specs or eye-diagram mask to ensure that our DUTs will still perform under adverse conditions. For receiver testing, we add impairments to ensure that the device still works or to discover when the device stops working. Disciplined margin testing informs us of the operating limits of our system with impaired signals.

Simple impairments like varying amplitude and frequencies will stress a receiver. At the next level, you should vary the input timing and also the input slew rate or rise times. The more subtle effects come from channel impairments like cross-talk, power supply filtering, and bandwidth degradation. To create bandwidth degradation, you need to be able to add ISI/DDj/PDj to the receiver input. To test cross-talk and switching supply immunity, you need to add Pj/Sj. Silicon effects can be tested by adding Rj until the receiver fails.

Every one of us validates our designs to ensure that they pass core specifications. However, we should also know under what conditions our designs will flat out fail. Our customers will always ensure that happens either by not adhering to design guidelines or not operating our devices within the recommended operating conditions. In the interest of learning how you deal with signal integrity margin in your products, it would be great to hear from you how your customers have “stressed” your designs.